Chisel3 compatibility potpourri

2015-07-30 23:52:42 -07:00
parent db7258f887
commit 57930e8a26
5 changed files with 5 additions and 5 deletions
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@ -306,7 +306,7 @@ class CSRFile extends CoreModule
    reg_mstatus.prv2 := reg_mstatus.prv1
    reg_mstatus.ie2 := reg_mstatus.ie1

-    reg_mepc := io.pc & SInt(-coreInstBytes)
+    reg_mepc := ~(~io.pc | (coreInstBytes-1))
    reg_mcause := io.cause
    when (csr_xcpt) {
      reg_mcause := Causes.illegal_instruction