riscv/rocket-chip
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Chisel3 compatibility potpourri

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Andrew Waterman committed 2015-07-30 23:53:02 -07:00
1 parent db7258f887
commit 57930e8a26
5 files changed
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rocket/src/main/scala/csr.scala
+1 -1
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@@ -306,7 +306,7 @@ class CSRFile extends CoreModule
reg_mstatus.prv2 := reg_mstatus.prv1
reg_mstatus.ie2 := reg_mstatus.ie1
reg_mepc := io.pc & SInt(-coreInstBytes)
reg_mepc := ~(~io.pc | (coreInstBytes-1))
reg_mcause := io.cause
when (csr_xcpt) {
reg_mcause := Causes.illegal_instruction