riscv/rocket-chip
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rejigger htif to use UncoreConfiguration

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This commit is contained in:
Andrew Waterman 2012-10-18 17:26:03 -07:00
parent e2eb7ce8e9
commit 5773cbb68a
6 changed files with 17 additions and 14 deletions
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2
rocket/src/main/scala/cpu.scala
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@ -7,7 +7,7 @@ import hwacha._
class ioRocket(implicit conf: RocketConfiguration) extends Bundle class ioRocket(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new ioHTIF val host = new ioHTIF(conf.ntiles)
val imem = new IOCPUFrontend val imem = new IOCPUFrontend
val vimem = new IOCPUFrontend val vimem = new IOCPUFrontend
val dmem = new ioHellaCache val dmem = new ioHellaCache

2
rocket/src/main/scala/dpath.scala
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@ -8,7 +8,7 @@ import hwacha._
class ioDpathAll(implicit conf: RocketConfiguration) extends Bundle class ioDpathAll(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new ioHTIF val host = new ioHTIF(conf.ntiles)
val ctrl = new ioCtrlDpath().flip val ctrl = new ioCtrlDpath().flip
val dmem = new ioHellaCache val dmem = new ioHellaCache
val dtlb = new ioDTLB_CPU_req_bundle().asOutput() val dtlb = new ioDTLB_CPU_req_bundle().asOutput()

2
rocket/src/main/scala/dpath_util.scala
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@ -55,7 +55,7 @@ class rocketDpathBTB(entries: Int) extends Component
class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new ioHTIF val host = new ioHTIF(conf.ntiles)
val r = new ioReadPort(); val r = new ioReadPort();
val w = new ioWritePort(); val w = new ioWritePort();

15
rocket/src/main/scala/htif.scala
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@ -10,8 +10,10 @@ class ioDebug extends Bundle
val error_mode = Bool(OUTPUT); val error_mode = Bool(OUTPUT);
} }
class ioHost(w: Int) extends Bundle class ioHost(val w: Int) extends Bundle
{ {
val clk = Bool(OUTPUT)
val clk_edge = Bool(OUTPUT)
val in = new FIFOIO()(Bits(width = w)).flip val in = new FIFOIO()(Bits(width = w)).flip
val out = new FIFOIO()(Bits(width = w)) val out = new FIFOIO()(Bits(width = w))
} }
@ -23,21 +25,21 @@ class PCRReq extends Bundle
val data = Bits(width = 64) val data = Bits(width = 64)
} }
class ioHTIF(implicit conf: RocketConfiguration) extends Bundle class ioHTIF(ntiles: Int) extends Bundle
{ {
val reset = Bool(INPUT) val reset = Bool(INPUT)
val debug = new ioDebug val debug = new ioDebug
val pcr_req = (new FIFOIO) { new PCRReq }.flip val pcr_req = (new FIFOIO) { new PCRReq }.flip
val pcr_rep = (new FIFOIO) { Bits(width = 64) } val pcr_rep = (new FIFOIO) { Bits(width = 64) }
val ipi_req = (new FIFOIO) { Bits(width = log2Up(conf.ntiles)) } val ipi_req = (new FIFOIO) { Bits(width = log2Up(ntiles)) }
val ipi_rep = (new FIFOIO) { Bool() }.flip val ipi_rep = (new FIFOIO) { Bool() }.flip
} }
class rocketHTIF(w: Int)(implicit conf: RocketConfiguration) extends Component class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val host = new ioHost(w) val host = new ioHost(w)
val cpu = Vec(conf.ntiles) { new ioHTIF().flip } val cpu = Vec(conf.ntiles) { new ioHTIF(conf.ntiles).flip }
val mem = new ioTileLink val mem = new ioTileLink
} }
@ -178,7 +180,8 @@ class rocketHTIF(w: Int)(implicit conf: RocketConfiguration) extends Component
} }
x_init.io.enq.valid := state === state_mem_req x_init.io.enq.valid := state === state_mem_req
val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3) val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
x_init.io.enq.bits := Mux(cmd === cmd_writemem, conf.co.getUncachedWriteTransactionInit(init_addr, UFix(0)), conf.co.getUncachedReadTransactionInit(init_addr, UFix(0))) val co = conf.co.asInstanceOf[CoherencePolicyWithUncached]
x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteTransactionInit(init_addr, UFix(0)), co.getUncachedReadTransactionInit(init_addr, UFix(0)))
io.mem.xact_init <> x_init.io.deq io.mem.xact_init <> x_init.io.deq
io.mem.xact_init_data.valid:= state === state_mem_wdata io.mem.xact_init_data.valid:= state === state_mem_wdata
io.mem.xact_init_data.bits.data := mem_req_data io.mem.xact_init_data.bits.data := mem_req_data

2
rocket/src/main/scala/tile.scala
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@ -9,7 +9,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends
{ {
val io = new Bundle { val io = new Bundle {
val tilelink = new ioTileLink val tilelink = new ioTileLink
val host = new ioHTIF val host = new ioHTIF(conf.ntiles)
} }
val cpu = new rocketProc val cpu = new rocketProc

8
rocket/src/main/scala/top.scala
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@ -25,16 +25,16 @@ class Top extends Component
else new MICoherence else new MICoherence
} }
implicit val rconf = RocketConfiguration(NTILES, co) implicit val rconf = RocketConfiguration(NTILES, co)
implicit val uconf = UncoreConfiguration(NTILES+1, log2Up(NTILES)+1) implicit val uconf = UncoreConfiguration(NTILES+1, log2Up(NTILES)+1, co)
val io = new Bundle { val io = new Bundle {
val debug = new ioDebug val debug = new ioDebug
val host = new ioHost(HTIF_WIDTH) val host = new ioHost(16)
val mem = new ioMemPipe val mem = new ioMemPipe
} }
val htif = new rocketHTIF(HTIF_WIDTH) val htif = new rocketHTIF(io.host.w)
val hub = new CoherenceHubBroadcast(co) val hub = new CoherenceHubBroadcast
hub.io.tiles(NTILES) <> htif.io.mem hub.io.tiles(NTILES) <> htif.io.mem
io.host <> htif.io.host io.host <> htif.io.host