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first and last on HasTileLinkData

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This commit is contained in:
Henry Cook 2016-03-01 15:45:35 -08:00
parent 4acdc67485
commit 57370bdf49
3 changed files with 7 additions and 13 deletions
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4
uncore/src/main/scala/cache.scala
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@ -789,9 +789,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
} }
// Enqueue some metadata information that we'll use to make coherence updates with later // Enqueue some metadata information that we'll use to make coherence updates with later
ignt_q.io.enq.valid := Mux(io.iacq().hasMultibeatData(), ignt_q.io.enq.valid := io.inner.acquire.fire() && io.iacq().first()
io.inner.acquire.fire() && io.iacq().addr_beat === UInt(0),
io.inner.acquire.fire())
ignt_q.io.enq.bits := io.iacq() ignt_q.io.enq.bits := io.iacq()
// Track whether any beats are missing from a PutBlock // Track whether any beats are missing from a PutBlock

14
uncore/src/main/scala/converters.scala
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@ -275,12 +275,6 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
val out = new ClientUncachedTileLinkIO val out = new ClientUncachedTileLinkIO
} }
def needsRoqEnq(channel: HasTileLinkData): Bool =
!channel.hasMultibeatData() || channel.addr_beat === UInt(0)
def needsRoqDeq(channel: HasTileLinkData): Bool =
!channel.hasMultibeatData() || channel.addr_beat === UInt(tlDataBeats - 1)
val acqArb = Module(new LockingRRArbiter(new Acquire, 2, tlDataBeats, val acqArb = Module(new LockingRRArbiter(new Acquire, 2, tlDataBeats,
Some((acq: Acquire) => acq.hasMultibeatData()))) Some((acq: Acquire) => acq.hasMultibeatData())))
@ -294,8 +288,8 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
val irel = io.in.release.bits val irel = io.in.release.bits
val ognt = io.out.grant.bits val ognt = io.out.grant.bits
val acq_roq_enq = needsRoqEnq(iacq) val acq_roq_enq = iacq.first()
val rel_roq_enq = needsRoqEnq(irel) val rel_roq_enq = irel.first()
val acq_roq_ready = !acq_roq_enq || acqRoq.io.enq.ready val acq_roq_ready = !acq_roq_enq || acqRoq.io.enq.ready
val rel_roq_ready = !rel_roq_enq || relRoq.io.enq.ready val rel_roq_ready = !rel_roq_enq || relRoq.io.enq.ready
@ -342,10 +336,10 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
io.out.acquire <> acqArb.io.out io.out.acquire <> acqArb.io.out
acqRoq.io.deq.valid := io.out.grant.fire() && needsRoqDeq(ognt) acqRoq.io.deq.valid := io.out.grant.fire() && ognt.last()
acqRoq.io.deq.tag := ognt.client_xact_id acqRoq.io.deq.tag := ognt.client_xact_id
relRoq.io.deq.valid := io.out.grant.fire() && needsRoqDeq(ognt) relRoq.io.deq.valid := io.out.grant.fire() && ognt.last()
relRoq.io.deq.tag := ognt.client_xact_id relRoq.io.deq.tag := ognt.client_xact_id
val gnt_builtin = acqRoq.io.deq.data val gnt_builtin = acqRoq.io.deq.data

2
uncore/src/main/scala/tilelink.scala
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@ -132,6 +132,8 @@ trait HasTileLinkData extends HasTileLinkBeatId {
def hasData(dummy: Int = 0): Bool def hasData(dummy: Int = 0): Bool
def hasMultibeatData(dummy: Int = 0): Bool def hasMultibeatData(dummy: Int = 0): Bool
def first(dummy: Int = 0): Bool = Mux(hasMultibeatData(), addr_beat === UInt(0), Bool(true))
def last(dummy: Int = 0): Bool = Mux(hasMultibeatData(), addr_beat === UInt(tlDataBeats-1), Bool(true))
} }
/** An entire cache block of data */ /** An entire cache block of data */