From 57370bdf49aca8817fac8f68cef22d65f9ccc045 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@eecs.berkeley.edu>
Date: Tue, 1 Mar 2016 15:45:35 -0800
Subject: [PATCH] first and last on HasTileLinkData

---
 uncore/src/main/scala/cache.scala      |  4 +---
 uncore/src/main/scala/converters.scala | 14 ++++----------
 uncore/src/main/scala/tilelink.scala   |  2 ++
 3 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/uncore/src/main/scala/cache.scala b/uncore/src/main/scala/cache.scala
index 5fe47a82..338f8f88 100644
--- a/uncore/src/main/scala/cache.scala
+++ b/uncore/src/main/scala/cache.scala
@@ -789,9 +789,7 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
   }
 
   // Enqueue some metadata information that we'll use to make coherence updates with later
-  ignt_q.io.enq.valid := Mux(io.iacq().hasMultibeatData(),
-                             io.inner.acquire.fire() && io.iacq().addr_beat === UInt(0),
-                             io.inner.acquire.fire())
+  ignt_q.io.enq.valid := io.inner.acquire.fire() && io.iacq().first()
   ignt_q.io.enq.bits := io.iacq()
 
   // Track whether any beats are missing from a PutBlock
diff --git a/uncore/src/main/scala/converters.scala b/uncore/src/main/scala/converters.scala
index e626a4a7..4900a253 100644
--- a/uncore/src/main/scala/converters.scala
+++ b/uncore/src/main/scala/converters.scala
@@ -275,12 +275,6 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
     val out = new ClientUncachedTileLinkIO
   }
 
-  def needsRoqEnq(channel: HasTileLinkData): Bool =
-    !channel.hasMultibeatData() || channel.addr_beat === UInt(0)
-
-  def needsRoqDeq(channel: HasTileLinkData): Bool =
-    !channel.hasMultibeatData() || channel.addr_beat === UInt(tlDataBeats - 1)
-
   val acqArb = Module(new LockingRRArbiter(new Acquire, 2, tlDataBeats,
     Some((acq: Acquire) => acq.hasMultibeatData())))
 
@@ -294,8 +288,8 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
   val irel = io.in.release.bits
   val ognt = io.out.grant.bits
 
-  val acq_roq_enq = needsRoqEnq(iacq)
-  val rel_roq_enq = needsRoqEnq(irel)
+  val acq_roq_enq = iacq.first()
+  val rel_roq_enq = irel.first()
 
   val acq_roq_ready = !acq_roq_enq || acqRoq.io.enq.ready
   val rel_roq_ready = !rel_roq_enq || relRoq.io.enq.ready
@@ -342,10 +336,10 @@ class ClientTileLinkIOUnwrapper(implicit p: Parameters) extends TLModule()(p) {
 
   io.out.acquire <> acqArb.io.out
 
-  acqRoq.io.deq.valid := io.out.grant.fire() && needsRoqDeq(ognt)
+  acqRoq.io.deq.valid := io.out.grant.fire() && ognt.last()
   acqRoq.io.deq.tag := ognt.client_xact_id
 
-  relRoq.io.deq.valid := io.out.grant.fire() && needsRoqDeq(ognt)
+  relRoq.io.deq.valid := io.out.grant.fire() && ognt.last()
   relRoq.io.deq.tag := ognt.client_xact_id
 
   val gnt_builtin = acqRoq.io.deq.data
diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala
index f5ac25de..1969f259 100644
--- a/uncore/src/main/scala/tilelink.scala
+++ b/uncore/src/main/scala/tilelink.scala
@@ -132,6 +132,8 @@ trait HasTileLinkData extends HasTileLinkBeatId {
 
   def hasData(dummy: Int = 0): Bool
   def hasMultibeatData(dummy: Int = 0): Bool
+  def first(dummy: Int = 0): Bool = Mux(hasMultibeatData(), addr_beat === UInt(0), Bool(true))
+  def last(dummy: Int = 0): Bool = Mux(hasMultibeatData(), addr_beat === UInt(tlDataBeats-1), Bool(true))
 }
 
 /** An entire cache block of data */