riscv/rocket-chip
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get unit tests working again

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This commit is contained in:
Howard Mao 2016-08-10 11:23:07 -07:00
parent 0ee1ce4366
commit 571d579b86
3 changed files with 16 additions and 8 deletions
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2
junctions/src/main/scala/unittests/UnitTest.scala
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@ -38,6 +38,8 @@ class UnitTestSuite(implicit p: Parameters) extends Module {
} }
val timer = Module(new Timer(1000, tests.size)) val timer = Module(new Timer(1000, tests.size))
timer.io.start.valid := Bool(false)
timer.io.stop.valid := Bool(false)
tests.zipWithIndex.foreach { case (mod, i) => tests.zipWithIndex.foreach { case (mod, i) =>
mod.io.start := (state === s_start) && test_idx === UInt(i) mod.io.start := (state === s_start) && test_idx === UInt(i)

6
uncore/src/main/scala/tilelink/Definitions.scala
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@ -399,6 +399,10 @@ object Acquire {
} }
def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).asUInt def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).asUInt
def fullOperandSize(implicit p: Parameters) = {
val dataBits = p(TLKey(p(TLId))).dataBitsPerBeat
UInt(log2Ceil(dataBits / 8))
}
// Most generic constructor // Most generic constructor
def apply( def apply(
@ -477,6 +481,7 @@ object Get {
client_xact_id = client_xact_id, client_xact_id = client_xact_id,
addr_block = addr_block, addr_block = addr_block,
addr_beat = addr_beat, addr_beat = addr_beat,
operand_size = Acquire.fullOperandSize,
opcode = M_XRD, opcode = M_XRD,
alloc = alloc) alloc = alloc)
} }
@ -519,6 +524,7 @@ object GetBlock {
a_type = Acquire.getBlockType, a_type = Acquire.getBlockType,
client_xact_id = client_xact_id, client_xact_id = client_xact_id,
addr_block = addr_block, addr_block = addr_block,
operand_size = Acquire.fullOperandSize,
opcode = M_XRD, opcode = M_XRD,
alloc = alloc) alloc = alloc)
} }

16
uncore/src/main/scala/unittests/Drivers.scala
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@ -313,18 +313,18 @@ class PutAtomicDriver(implicit p: Parameters) extends Driver()(p) {
client_xact_id = UInt(0), client_xact_id = UInt(0),
addr_block = UInt(0), addr_block = UInt(0),
addr_beat = UInt(0), addr_beat = UInt(0),
// Put 15 in bytes 3:2 // Put 15 in bytes 7:4
data = UInt(15 << 16), data = UInt(15L << 32),
wmask = Some(UInt(0x0c))) wmask = Some(UInt(0xf0)))
val amo_acquire = PutAtomic( val amo_acquire = PutAtomic(
client_xact_id = UInt(0), client_xact_id = UInt(0),
addr_block = UInt(0), addr_block = UInt(0),
addr_beat = UInt(0), addr_beat = UInt(0),
addr_byte = UInt(2), addr_byte = UInt(4),
atomic_opcode = M_XA_ADD, atomic_opcode = M_XA_ADD,
operand_size = UInt(log2Ceil(16 / 8)), operand_size = UInt(log2Ceil(32 / 8)),
data = UInt(3 << 16)) data = UInt(3L << 32))
val get_acquire = Get( val get_acquire = Get(
client_xact_id = UInt(0), client_xact_id = UInt(0),
@ -351,8 +351,8 @@ class PutAtomicDriver(implicit p: Parameters) extends Driver()(p) {
when (state === s_get) { state := s_done } when (state === s_get) { state := s_done }
} }
assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() || assert(!io.mem.grant.valid || state =/= s_get ||
io.mem.grant.bits.data(31, 16) === UInt(18)) io.mem.grant.bits.data(63, 32) === UInt(18))
} }
class PrefetchDriver(implicit p: Parameters) extends Driver()(p) { class PrefetchDriver(implicit p: Parameters) extends Driver()(p) {