From 571d579b86fe3c4b25e70f1c01a14fb659a74876 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 10 Aug 2016 11:23:07 -0700
Subject: [PATCH] get unit tests working again

---
 .../src/main/scala/unittests/UnitTest.scala      |  2 ++
 uncore/src/main/scala/tilelink/Definitions.scala |  6 ++++++
 uncore/src/main/scala/unittests/Drivers.scala    | 16 ++++++++--------
 3 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/junctions/src/main/scala/unittests/UnitTest.scala b/junctions/src/main/scala/unittests/UnitTest.scala
index 6e660ba4..eeb308ca 100644
--- a/junctions/src/main/scala/unittests/UnitTest.scala
+++ b/junctions/src/main/scala/unittests/UnitTest.scala
@@ -38,6 +38,8 @@ class UnitTestSuite(implicit p: Parameters) extends Module {
   }
 
   val timer = Module(new Timer(1000, tests.size))
+  timer.io.start.valid := Bool(false)
+  timer.io.stop.valid := Bool(false)
 
   tests.zipWithIndex.foreach { case (mod, i) =>
     mod.io.start := (state === s_start) && test_idx === UInt(i)
diff --git a/uncore/src/main/scala/tilelink/Definitions.scala b/uncore/src/main/scala/tilelink/Definitions.scala
index ff3a6067..914d9a44 100644
--- a/uncore/src/main/scala/tilelink/Definitions.scala
+++ b/uncore/src/main/scala/tilelink/Definitions.scala
@@ -399,6 +399,10 @@ object Acquire {
   }
 
   def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).asUInt
+  def fullOperandSize(implicit p: Parameters) = {
+    val dataBits = p(TLKey(p(TLId))).dataBitsPerBeat
+    UInt(log2Ceil(dataBits / 8))
+  }
 
   // Most generic constructor
   def apply(
@@ -477,6 +481,7 @@ object Get {
       client_xact_id = client_xact_id,
       addr_block = addr_block,
       addr_beat = addr_beat,
+      operand_size = Acquire.fullOperandSize,
       opcode = M_XRD,
       alloc = alloc)
   }
@@ -519,6 +524,7 @@ object GetBlock {
       a_type = Acquire.getBlockType,
       client_xact_id = client_xact_id, 
       addr_block = addr_block,
+      operand_size = Acquire.fullOperandSize,
       opcode = M_XRD,
       alloc = alloc)
   }
diff --git a/uncore/src/main/scala/unittests/Drivers.scala b/uncore/src/main/scala/unittests/Drivers.scala
index b23b9e95..09748a2a 100644
--- a/uncore/src/main/scala/unittests/Drivers.scala
+++ b/uncore/src/main/scala/unittests/Drivers.scala
@@ -313,18 +313,18 @@ class PutAtomicDriver(implicit p: Parameters) extends Driver()(p) {
     client_xact_id = UInt(0),
     addr_block = UInt(0),
     addr_beat = UInt(0),
-    // Put 15 in bytes 3:2
-    data = UInt(15 << 16),
-    wmask = Some(UInt(0x0c)))
+    // Put 15 in bytes 7:4
+    data = UInt(15L << 32),
+    wmask = Some(UInt(0xf0)))
 
   val amo_acquire = PutAtomic(
     client_xact_id = UInt(0),
     addr_block = UInt(0),
     addr_beat = UInt(0),
-    addr_byte = UInt(2),
+    addr_byte = UInt(4),
     atomic_opcode = M_XA_ADD,
-    operand_size = UInt(log2Ceil(16 / 8)),
-    data = UInt(3 << 16))
+    operand_size = UInt(log2Ceil(32 / 8)),
+    data = UInt(3L << 32))
 
   val get_acquire = Get(
     client_xact_id = UInt(0),
@@ -351,8 +351,8 @@ class PutAtomicDriver(implicit p: Parameters) extends Driver()(p) {
     when (state === s_get) { state := s_done }
   }
 
-  assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
-         io.mem.grant.bits.data(31, 16) === UInt(18))
+  assert(!io.mem.grant.valid || state =/= s_get ||
+         io.mem.grant.bits.data(63, 32) === UInt(18))
 }
 
 class PrefetchDriver(implicit p: Parameters) extends Driver()(p) {