riscv/rocket-chip
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coreplex: MemoryBusParams.beatBytes also based on XLen

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Henry Cook committed 2017-09-13 11:25:42 -07:00
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commit 56dae946b6
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src/main/scala/coreplex/Configs.scala
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@@ -22,7 +22,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
// Interconnect parameters
case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case MemoryBusKey => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes))
case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
// Additional device Parameters
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")