From 56dae946b6199f0abd3960a673bba51e0f615042 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 8 Sep 2017 19:08:53 -0700 Subject: [PATCH] coreplex: MemoryBusParams.beatBytes also based on XLen --- src/main/scala/coreplex/Configs.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala index 969982f2..46865cde 100644 --- a/src/main/scala/coreplex/Configs.scala +++ b/src/main/scala/coreplex/Configs.scala @@ -22,7 +22,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => { // Interconnect parameters case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) - case MemoryBusKey => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes)) + case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) // Additional device Parameters case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff))) case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")