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coreplex: MemoryBusParams.beatBytes also based on XLen

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This commit is contained in:
Henry Cook 2017-09-08 19:08:53 -07:00
parent b86f4b9bb7
commit 56dae946b6
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/Configs.scala
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@ -22,7 +22,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
// Interconnect parameters // Interconnect parameters
case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes)) case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
case MemoryBusKey => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes)) case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
// Additional device Parameters // Additional device Parameters
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff))) case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img") case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")