riscv/rocket-chip
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Merge branch 'tilelink-data'

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This commit is contained in:
Henry Cook
2013-05-23 14:14:40 -07:00
parent fe9adfe71b 12205b9684
commit 569d8fd796
5 changed files with 23 additions and 80 deletions
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14
rocket/src/main/scala/nbdcache.scala
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@ -937,11 +937,11 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
mshr.io.mem_grant.bits := io.mem.grant.bits
when (mshr.io.req.fire()) { replacer.miss }
io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_req)
//TODO io.mem.acquire_data should be connected to uncached store data generator
//io.mem.acquire_data <> FIFOedLogicalNetworkIOWrapper(TODO)
io.mem.acquire_data.valid := Bool(false)
io.mem.acquire_data.bits.payload.data := UFix(0)
io.mem.acquire.meta <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_req)
//TODO io.mem.acquire.data should be connected to uncached store data generator
//io.mem.acquire.data <> FIFOedLogicalNetworkIOWrapper(TODO)
io.mem.acquire.data.valid := Bool(false)
io.mem.acquire.data.bits.payload.data := UFix(0)
// replays
readArb.io.in(1).valid := mshr.io.replay.valid
@ -954,7 +954,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
// probes
val releaseArb = (new Arbiter(2)) { new Release }
FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release
FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release.meta
val probe = FIFOedLogicalNetworkIOUnwrapper(io.mem.probe)
prober.io.req.valid := probe.valid && !lrsc_valid
@ -982,7 +982,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio
wb.io.data_req <> readArb.io.in(2)
wb.io.data_resp := s2_data_corrected
releaseArb.io.in(0) <> wb.io.release
FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release_data
FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release.data
// store->load bypassing
val s4_valid = Reg(s3_valid, resetVal = Bool(false))