diff --git a/rocket/src/main/scala/config.scala b/rocket/src/main/scala/config.scala deleted file mode 100644 index 13d7344a..00000000 --- a/rocket/src/main/scala/config.scala +++ /dev/null @@ -1,56 +0,0 @@ -package rocket -package config - -import java.io.File -import java.io.FileInputStream -import java.util.Properties -import scala.util.{Properties => SProperties} - -class Config(props: Properties) { - private val msg = "Configuration is missing requested parameter " - def getInt(name: String): Int = Option(props.getProperty(name).toInt).getOrElse(sys.error(msg+name)) - def getString(name: String): String = Option(props.getProperty(name)).getOrElse(sys.error(msg+name)) - def getBoolean(name: String): Boolean = Option(props.getProperty(name).toBoolean).getOrElse(sys.error(msg+name)) - def apply(name: String): Int = getInt(name) -} - -object Config { - - lazy val internal_config = getConfig() - - def apply(name: String) = internal_config(name) - - private def getConfig(): Config = { - - val filePath0 = - SProperties - .envOrNone("ROCKET_CONFIG") - .orElse(SProperties.propOrNone("rocket.config")) - if (filePath0.isEmpty) - Console.err.println(""" - | WARNING: Could not find configuration file to load. - | Options are: - | (1) Set environmental variable ROCKET_CONFIG to the config file path - | (2) Set system property rocket.config to the config file path - | Using default values for config. - """.stripMargin) - - val filePath = - filePath0.flatMap(fp => { - val f = new File(fp) - if (!f.isFile) { - Console.err.println(""" - | WARNING: File '%s' is not a valid file path - | Using default values for config - """.format(fp).stripMargin) - None - } else Some(fp) - }) - - val props = new Properties() - filePath.map(fp => props.load(new FileInputStream(fp))) - new Config(props) - } - -} - diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 6a872715..8a999419 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -139,7 +139,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w when (state === state_mem_req && x_init.io.enq.ready) { state := Mux(cmd === cmd_writemem, state_mem_wdata, state_mem_rdata) } - when (state === state_mem_wdata && io.mem.acquire_data.ready) { + when (state === state_mem_wdata && io.mem.acquire.data.ready) { when (mem_cnt.andR) { state := state_mem_wresp } @@ -185,15 +185,15 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component w val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3) val co = conf.co.asInstanceOf[CoherencePolicyWithUncached] x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteAcquire(init_addr, UFix(0)), co.getUncachedReadAcquire(init_addr, UFix(0))) - io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq, UFix(conf.ln.nClients), UFix(0)) - io.mem.acquire_data.valid := state === state_mem_wdata - io.mem.acquire_data.bits.payload.data := mem_req_data + io.mem.acquire.meta <> FIFOedLogicalNetworkIOWrapper(x_init.io.deq, UFix(conf.ln.nClients), UFix(0)) + io.mem.acquire.data.valid := state === state_mem_wdata + io.mem.acquire.data.bits.payload.data := mem_req_data io.mem.grant_ack.valid := (state === state_mem_finish) && mem_needs_ack io.mem.grant_ack.bits.payload.master_xact_id := mem_gxid io.mem.grant_ack.bits.header.dst := mem_gsrc io.mem.probe.ready := Bool(false) - io.mem.release.valid := Bool(false) - io.mem.release_data.valid := Bool(false) + io.mem.release.meta.valid := Bool(false) + io.mem.release.data.valid := Bool(false) val pcrReadData = Reg{Bits(width = io.cpu(0).pcr_rep.bits.getWidth)} for (i <- 0 until conf.ln.nClients) { diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 374bae6b..31810b60 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -248,9 +248,9 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte // output signals io.resp.valid := s2_hit - io.mem.acquire.valid := (state === s_request) && finish_q.io.enq.ready - io.mem.acquire.bits.payload := c.co.getUncachedReadAcquire(s2_addr >> UFix(c.offbits), UFix(0)) - io.mem.acquire_data.valid := Bool(false) + io.mem.acquire.meta.valid := (state === s_request) && finish_q.io.enq.ready + io.mem.acquire.meta.bits.payload := c.co.getUncachedReadAcquire(s2_addr >> UFix(c.offbits), UFix(0)) + io.mem.acquire.data.valid := Bool(false) io.mem.grant_ack <> FIFOedLogicalNetworkIOWrapper(finish_q.io.deq) io.mem.grant.ready := Bool(true) @@ -261,7 +261,7 @@ class ICache(implicit c: ICacheConfig, lnconf: LogicalNetworkConfiguration) exte invalidated := Bool(false) } is (s_request) { - when (io.mem.acquire.ready && finish_q.io.enq.ready) { state := s_refill_wait } + when (io.mem.acquire.meta.ready && finish_q.io.enq.ready) { state := s_refill_wait } } is (s_refill_wait) { when (io.mem.grant.valid) { state := s_refill } diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index bfd9c83c..78dbb61e 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -937,11 +937,11 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio mshr.io.mem_grant.bits := io.mem.grant.bits when (mshr.io.req.fire()) { replacer.miss } - io.mem.acquire <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_req) - //TODO io.mem.acquire_data should be connected to uncached store data generator - //io.mem.acquire_data <> FIFOedLogicalNetworkIOWrapper(TODO) - io.mem.acquire_data.valid := Bool(false) - io.mem.acquire_data.bits.payload.data := UFix(0) + io.mem.acquire.meta <> FIFOedLogicalNetworkIOWrapper(mshr.io.mem_req) + //TODO io.mem.acquire.data should be connected to uncached store data generator + //io.mem.acquire.data <> FIFOedLogicalNetworkIOWrapper(TODO) + io.mem.acquire.data.valid := Bool(false) + io.mem.acquire.data.bits.payload.data := UFix(0) // replays readArb.io.in(1).valid := mshr.io.replay.valid @@ -954,7 +954,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio // probes val releaseArb = (new Arbiter(2)) { new Release } - FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release + FIFOedLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release.meta val probe = FIFOedLogicalNetworkIOUnwrapper(io.mem.probe) prober.io.req.valid := probe.valid && !lrsc_valid @@ -982,7 +982,7 @@ class HellaCache(implicit conf: DCacheConfig, lnconf: LogicalNetworkConfiguratio wb.io.data_req <> readArb.io.in(2) wb.io.data_resp := s2_data_corrected releaseArb.io.in(0) <> wb.io.release - FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release_data + FIFOedLogicalNetworkIOWrapper(wb.io.release_data) <> io.mem.release.data // store->load bypassing val s4_valid = Reg(s3_valid, resetVal = Bool(false)) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index b073f9be..2c6cd558 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -40,20 +40,19 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon val icache = new Frontend()(confIn.icache, lnConf) val dcache = new HellaCache - val arbiter = new UncachedTileLinkIOArbiter(memPorts) + val arbiter = new UncachedTileLinkIOArbiter(memPorts, confIn.dcache.co) arbiter.io.in(dcachePortId) <> dcache.io.mem arbiter.io.in(icachePortId) <> icache.io.mem io.tilelink.acquire <> arbiter.io.out.acquire - io.tilelink.acquire_data <> arbiter.io.out.acquire_data arbiter.io.out.grant <> io.tilelink.grant io.tilelink.grant_ack <> arbiter.io.out.grant_ack dcache.io.mem.probe <> io.tilelink.probe - io.tilelink.release_data <> dcache.io.mem.release_data - io.tilelink.release.valid := dcache.io.mem.release.valid - dcache.io.mem.release.ready := io.tilelink.release.ready - io.tilelink.release.bits := dcache.io.mem.release.bits - io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UFix(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client) + io.tilelink.release.data <> dcache.io.mem.release.data + io.tilelink.release.meta.valid := dcache.io.mem.release.meta.valid + dcache.io.mem.release.meta.ready := io.tilelink.release.meta.ready + io.tilelink.release.meta.bits := dcache.io.mem.release.meta.bits + io.tilelink.release.meta.bits.payload.client_xact_id := Cat(dcache.io.mem.release.meta.bits.payload.client_xact_id, UFix(dcachePortId, log2Up(memPorts))) // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client) /*val ioSubBundles = io.tilelink.getClass.getMethods.filter( x => classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m =>