Purge legacy HTIF things
The SCR file is gone, too, because it was tightly coupled. The general concept could be revived as a module that somehow connects to the debug module.
This commit is contained in:
Andrew Waterman
parent
2d44be747a
commit
568bfa6c50
2
Makefrag
2
Makefrag
@ -64,7 +64,6 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
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params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm
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consts_header = $(generated_dir)/consts.$(CONFIG).h
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scr_header = $(generated_dir)/$(MODEL).$(CONFIG).scr_map.h
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$(consts_header): $(params_file)
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echo "#ifndef __CONST_H__" > $@
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echo "#define __CONST_H__" >> $@
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@ -80,4 +79,3 @@ $(consts_header_debug): $(params_file_debug)
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sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
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echo "#define TBFRAG \"$(MODEL).$(CONFIG).tb.cpp\"" >> $@
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echo "#endif // __CONST_H__" >> $@
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scr_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).scr_map.h
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142
README.md
142
README.md
@ -81,13 +81,27 @@ Similarly, to generate VLSI-synthesizable verilog (output will be in `vsim/gener
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$ cd vsim
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$ make verilog
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### Updating To A Newer Version Of Chisel
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To grab a newer version of chisel:
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### Keeping Your Repo Up-to-Date
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$ git submodule update --init
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$ cd chisel
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If you are trying to keep your repo up to date with this github repo,
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you also need to keep the submodules and tools up to date.
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$ # Get the newest versions of the files in this repo
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$ git pull origin master
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$ # Make sure the submodules have the correct versions
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$ git submodule update --init --recursive
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If riscv-tools version changes, you should recompile and install riscv-tools according to the directions in the [riscv-tools/README](https://github.com/riscv/riscv-tools/blob/master/README.md).
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$ cd riscv-tools
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$ ./build.sh
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If firrtl version changes and you are using Chisel3, you may need to clean and recompile:
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$ cd firrtl
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$ sbt clean
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$ sbt assembly
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## <a name="what"></a> What's in the Rocket chip generator repository?
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@ -101,11 +115,12 @@ at Berkeley, the ability to compose a subset of private and public
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sub-repositories on a per-chip basis is a killer feature of git
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submodule.
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So, which submodules are actually included in this chip's repository?
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### <a name="what_submodules"></a>The Submodules
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Here's a look at all the git submodules that are currently tracked in
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the rocket-chip repository:
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* **chisel**
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* **chisel2**
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([https://github.com/ucb-bar/chisel](https://github.com/ucb-bar/chisel)):
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At Berkeley, we write RTL in Chisel. For those who are not familiar
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with Chisel, please go take a look at
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@ -117,6 +132,17 @@ and hence it was easiest to use submodule to track bleeding edge commits
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to Chisel, which contained a bunch of new features and bug fixes. As
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Chisel gets more stable, we will likely replace this submodule with an
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external dependency.
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* **chisel3**
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([https://github.com/ucb-bar/chisel3](https://github.com/ucb-bar/chisel3)):
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Chisel3 is a newer version of Chisel, which is based on FIRRTL. The Chisel
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code in this repository is generally compatible with both Chisel2 and Chisel3.
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The [chisel3/README](https://github.com/ucb-bar/chisel3/blob/master/README.md).gives
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instructions on how to build your design with Chisel3 instead of Chisel2.
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* **firrtl**
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([https://github.com/ucb-bar/firrtl](https://github.com/ucb-bar/firrtl)):
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FIRRTL (Flexible Internal Representation for RTL) is the intermediate format
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which Chisel3 is based upon. The Chisel3 compiler generates a FIRRTL representation,
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from which the final product (Verilog code, C code, etc) is generated.
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* **rocket**
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([https://github.com/ucb-bar/rocket](https://github.com/ucb-bar/rocket)):
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The rocket repository holds the actual source code of the Rocket core.
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@ -129,8 +155,12 @@ core within a memory system and connects it to the outside world.
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([https://github.com/ucb-bar/uncore](https://github.com/ucb-bar/uncore)):
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This repository implements the uncore logic, such as the coherence hub
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(the agent that keeps multiple L1 D$ coherent). The definition of the
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coherent interfaces between tiles ("tilelink") and the interface to the
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host machine ("htif") also live in this repository.
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coherent interfaces between tiles ("tilelink") and the debug interface
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also live in this repository.
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* **junctions**
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([https://github.com/ucb-bar/junctions](https://github.com/ucb-bar/junctions)):
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This repository contains code and
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converters for various bus protocols and interfaces.
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* **hardfloat**
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([https://github.com/ucb-bar/berkeley-hardfloat](https://github.com/ucb-bar/berkeley-hardfloat)):
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This repository holds the parameterized IEEE 754-2008 compliant
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@ -142,6 +172,12 @@ has an additional bit) to handle subnormal numbers more efficiently in
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the processor. Please take a look at the
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[README](https://github.com/ucb-bar/berkeley-hardfloat/blob/master/README.md)
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in the repository for more information.
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* **context-dependent-environments**
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([https://github.com/ucb-bar/context-dependent-environments](https://github.com/ucb-bar/context-dependent-environments)):
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The rocket-chip Chisel code is highly parameterizable, and utilizes the classes in
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this subrepo to set and pass parameters to different levels of the design. Note that in
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Chisel2, this was handled by Chisel itself, but has been moved into a seperate
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library for use with Chisel3.
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* **dramsim2**
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([https://github.com/dramninjasUMD/DRAMSim2](https://github.com/dramninjasUMD/DRAMSim2)):
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Currently, the DRAM memory system is implemented in the testbench. We
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@ -155,9 +191,22 @@ committed in the rocket-chip repository.
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We tag a version of riscv-tools that works with the RTL committed in the
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rocket-chip repository. Once the software toolchain stabilizes, we
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might turn this submodule into an external dependency.
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* **groundtest**
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([https://github.com/ucb-bar/groundtest](https://github.com/ucb-bar/groundtest)):
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This repository contains code which can test the uncore by generating randomized
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instruction streams. It replaces the rocket processor with an instruction
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stream generator to stress-test the uncore portions of the design.
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* **torture**
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([https://github.com/ucb-bar/torture](https://github.com/ucb-bar/torture)):
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The torture test code is used to generate randomized instruction streams which
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are then run as code on the rocket core(s). These are constrained random tests
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to stress-test both the core and uncore portions of the design.
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Next, take a look at rocket-chip's src/main/scala directory. There are a
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couple Chisel source files including RocketChip.scala, which
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### <a name="what_toplevel"></a>The Submodules
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Next, take a look at rocket-chip's src/main/scala directory.
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This directory has the Chisel source files including the top level
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RocketChip.scala, which
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instantiates both a Rocket core and the uncore logic, and then glues
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them together. Here's a brief overview of source files found in the
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rocket-chip repository:
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@ -184,37 +233,46 @@ down to Verilog. Pretty neat huh?
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implements logic to interface with an arbitrary number of slow
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single-ended digital I/Os when implementing a test chip.
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Now you should take a look at the top-level I/O pins. Open up
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Take a look at the top-level I/O pins. Open up
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src/main/scala/RocketChip.scala, and search for TopIO. You will read the
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following (note, HostIO is defined in uncore/src/main/scala/htif.scala,
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and MemIO is defined in uncore/src/main/scala/memserdes.scala):
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following:
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class TopIO extends Bundle {
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val host = new HostIO
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val mem = new MemIO
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val mem_backup_en = Bool(INPUT)
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val in_mem_ready = Bool(OUTPUT)
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val in_mem_valid = Bool(INPUT)
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val out_mem_ready = Bool(INPUT)
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val out_mem_valid = Bool(OUTPUT)
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/** Top-level io for the chip */
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class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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with HasTopLevelParameters
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem_axi = Vec(nMemAXIChannels, new NastiIO)
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val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
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val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
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val debug = new DebugBusIO()(p).flip
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}
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There are 3 major I/O ports coming out of the top-level module:
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* **Host-target interface (HostIO)**: The host system talks to the
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There are 5 major I/O ports coming out of the top-level module:
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* **Host-target interface (host)**: The host system talks to the
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target machine via this host-target interface. We serialize a simple
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protocol over this parameterized interface. More details will come.
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* **High-performance memory interface (MemIO, mem\_backup\_en=false)**:
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When mem\_backup\_en is tied low, all memory requests from the processor
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comes out the MemIO port. The MemIO port uses the same uncore clock, and
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protocol over this parameterized interface. This interface is slated
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for removal in the near future.
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* **Debug interface (debug)**:
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The debug interface can be used to both debug the processor as
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it is executing, and to read and write memory. It is slated to repalce the
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host interface in the near future.
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* **High-performance memory interface (mem_*) **:
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Memory requests from the processor comes out the mem_* ports.
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Depending on the configuration of the design, these may be visible as
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AXI or AHB protocol. The mem_* port(s) uses the same uncore clock, and
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is intended to be connected to something on the same chip.
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* **Low-performance memory interface (parts of HostIO, in\_mem\_\*,
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out\_mem\_\*, mem\_backup\_en=true)**: When mem\_backup\_en is tied
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high, all memory requests from the processor comes out the
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low-performance memory interface. To save actual pins on a test chip, we
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multiplex the data pins of the host-target interface with the serialized
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low-performance memory port. That's the reason why you only see the
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control pins (in\_mem\_* and out\_mem\_*).
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* ** Memory mapped I/O interface (mmio_*) **:
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The optional mmio_* interfaces can be used to communicate with devices
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on the chip but outside of the rocket-chip boundary. Depending on the
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configuration of the design, these may be visible as AXI or AHB.
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* ** Interrupts interface (interrupts) **: This interface is used to
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deliver external interrupts to the processor core.
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Of course, there's a lot more in the actual submodules, but hopefully
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this would be enough to get you started with using the Rocket chip
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@ -227,7 +285,7 @@ list.
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Chisel can generate code for three targets: a high-performance
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cycle-accurate C++ emulator, Verilog optimized for FPGAs, and Verilog
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for VLSI. The Rocket chip generator can target all three backends. You
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for VLSI. The rocket-chip generator can target all three backends. You
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will need a Java runtime installed on your machine, since Chisel is
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overlaid on top of [Scala](http://www.scala-lang.org/). Chisel RTL (i.e.
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rocket-chip source code) is a Scala program executing on top of your
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@ -314,7 +372,7 @@ emulator/output/rv64ui-p-add.out:
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C0: 484 [1] pc=[0000000213c] W[r29=000000007fff8000][1] R[r31=ffffffff80007ffe] R[r31=0000000000000005] inst=[7fff8eb7] lui t3, 0x7fff8
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C0: 485 [0] pc=[00000002140] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000000] unknown
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This means at cycle 483, core 0, the first [1] shows that there's a
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The first [1] at cycle 483, core 0, shows that there's a
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valid instruction at PC 0x2138 in the writeback stage, which is
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0x002081b3 (add s1, ra, s0). The second [1] tells us that the register
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file is writing r3 with the corresponding value 0x7fff7fff. When the add
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@ -443,6 +501,18 @@ This parameterization is one of the many strengths of processor
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generators written in Chisel, and will be more detailed in a future blog
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post, so please stay tuned.
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To override specific configuration items, such as the number of external interrupts,
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you can create your own Configuration(s) and compose them with Config's ++ operator
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class WithNExtInterrupts extends Config (nExt: Int) {
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(pname, site, here) => pname match {
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case (NExtInterrupts => nExt)
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}
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}
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class MyConfig extends Config (new WithNExtInterrupts(16) ++ new DefaultSmallConfig)
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Then you can build as usual with CONFIG=MyConfig.
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## <a name="contributors"></a> Contributors
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- Scott Beamer
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@ -1,39 +0,0 @@
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// See LICENSE for license details.
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#ifndef _HTIF_EMULATOR_H
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#define _HTIF_EMULATOR_H
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#include <fesvr/htif_pthread.h>
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class htif_emulator_t : public htif_pthread_t
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{
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int memory_channel_mux_select;
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public:
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htif_emulator_t(const std::vector<std::string>& args)
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: htif_pthread_t(args),
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memory_channel_mux_select(0)
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{
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for (const auto& arg: args) {
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if (!strncmp(arg.c_str(), "+memory_channel_mux_select=", 27))
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memory_channel_mux_select = atoi(arg.c_str()+27);
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}
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}
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void set_clock_divisor(int divisor, int hold_cycles)
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{
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#ifdef UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR__OFFSET
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/* We only want to write the HTIF clock divisor SCR on targets where it
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* actually exists (there isn't one on the FPGA, for example). */
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write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR__OFFSET, divisor | hold_cycles << 16);
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#endif
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}
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void start()
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{
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set_clock_divisor(5, 2);
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htif_pthread_t::start();
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}
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};
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#endif
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@ -22,10 +22,10 @@ $(generated_dir_debug)/%.o: $(generated_dir_debug)/%.cpp $(generated_dir_debug)/
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$(CXX) $(CXXFLAGS) -I$(generated_dir_debug) -c -o $@ $<
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$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header) $(consts_header)
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$(CXX) $(CXXFLAGS) -include $(scr_header) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
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$(CXX) $(CXXFLAGS) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
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|
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$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header_debug) $(consts_header_debug)
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$(CXX) $(CXXFLAGS) -include $(scr_header_debug) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<
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$(CXX) $(CXXFLAGS) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<
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|
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$(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.$(CONFIG).h $(generated_dir)/%.$(CONFIG).prm: $(chisel_srcs)
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cd $(base_dir) && $(SBT) "project $(PROJECT)" "run $(CHISEL_ARGS) --noIoDebug"
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@ -69,12 +69,12 @@ $(emu): $(verilog) $(cppfiles) libdramsim.a $(consts_header) $(INSTALLED_VERILAT
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mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
|
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-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)"
|
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-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
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$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
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|
||||
$(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
|
||||
mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
|
||||
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG) --trace \
|
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-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
|
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-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)"
|
||||
-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)"
|
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$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
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|
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@ -39,7 +39,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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-CC "-include $(consts_header)" \
|
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-CC "-include $(scr_header)" \
|
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-e vcs_main \
|
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$(RISCV)/lib/libfesvr.so \
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$(sim_dir)/libdramsim.a \
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|
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@ -1 +1 @@
|
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Subproject commit e636d7a4ff1a6fe11f6fd4ee8ad2588becae68ae
|
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Subproject commit 146200e473bd969a4c1d5b9bf349f9b3b72adee8
|
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2
rocket
2
rocket
@ -1 +1 @@
|
||||
Subproject commit 781b814e1b333262eb78c5b62c6aabf4b6afc9d3
|
||||
Subproject commit 36e02ac94a8b2fbaa057bee37b2f7ed2a72dd227
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@ -108,12 +108,6 @@ class BaseConfig extends Config (
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lazy val innerDataBits = site(MIFDataBits)
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
|
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pname match {
|
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case HtifKey => HtifParameters(
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width = Dump("HTIF_WIDTH", 16),
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nSCR = 64,
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csrDataBits = site(XLen),
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offsetBits = site(CacheBlockOffsetBits),
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nCores = site(NTiles))
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//Memory Parameters
|
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case PAddrBits => 32
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case PgIdxBits => 12
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@ -312,7 +306,6 @@ class BaseConfig extends Config (
|
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case BankIdLSB => 0
|
||||
case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
|
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case UseHtifClockDiv => true
|
||||
case ConfigString => makeConfigString()
|
||||
case GlobalAddrMap => globalAddrMap
|
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case _ => throw new CDEMatchError
|
||||
@ -413,7 +406,6 @@ class WithRV32 extends Config(
|
||||
class FPGAConfig extends Config (
|
||||
(pname,site,here) => pname match {
|
||||
case NAcquireTransactors => 4
|
||||
case UseHtifClockDiv => false
|
||||
case _ => throw new CDEMatchError
|
||||
}
|
||||
)
|
||||
|
||||
@ -31,8 +31,6 @@ case object NOutstandingMemReqsPerChannel extends Field[Int]
|
||||
/** Number of exteral MMIO ports */
|
||||
case object NExtMMIOAXIChannels extends Field[Int]
|
||||
case object NExtMMIOAHBChannels extends Field[Int]
|
||||
/** Whether to divide HTIF clock */
|
||||
case object UseHtifClockDiv extends Field[Boolean]
|
||||
/** Function for building some kind of coherence manager agent */
|
||||
case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
|
||||
/** Function for building some kind of tile connected to a reset signal */
|
||||
@ -66,11 +64,6 @@ trait HasTopLevelParameters {
|
||||
lazy val mifAddrBits = p(MIFAddrBits)
|
||||
lazy val mifDataBeats = p(MIFDataBeats)
|
||||
lazy val xLen = p(XLen)
|
||||
lazy val nSCR = p(HtifKey).nSCR
|
||||
lazy val scrAddrBits = log2Up(nSCR)
|
||||
lazy val scrDataBits = 64
|
||||
lazy val scrDataBytes = scrDataBits / 8
|
||||
//require(lsb + log2Up(nBanks) < mifAddrBits)
|
||||
}
|
||||
|
||||
class MemBackupCtrlIO extends Bundle {
|
||||
@ -176,7 +169,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
|
||||
/** Wrapper around everything that isn't a Tile.
|
||||
*
|
||||
* Usually this is clocked and/or place-and-routed separately from the Tiles.
|
||||
* Contains the Host-Target InterFace module (HTIF).
|
||||
*/
|
||||
class Uncore(implicit val p: Parameters) extends Module
|
||||
with HasTopLevelParameters {
|
||||
|
||||
@ -5,7 +5,6 @@ package rocketchip
|
||||
import Chisel._
|
||||
import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
|
||||
import cde.{Parameters, ParameterDump, Config}
|
||||
import uncore.AllSCRFiles
|
||||
|
||||
abstract class RocketTestSuite {
|
||||
val dir: String
|
||||
@ -201,7 +200,4 @@ object TestGenerator extends App with FileSystemUtilities {
|
||||
val w = createOutputFile(configClassName + ".cst")
|
||||
w.write(world.getConstraints)
|
||||
w.close
|
||||
val scr_map_hdr = createOutputFile(topModuleName + "." + configClassName + ".scr_map.h")
|
||||
AllSCRFiles.foreach{ map => scr_map_hdr.write(map.as_c_header) }
|
||||
scr_map_hdr.close
|
||||
}
|
||||
|
||||
2
uncore
2
uncore
@ -1 +1 @@
|
||||
Subproject commit b92487d5934d9efba0e960466455c32c36874c81
|
||||
Subproject commit 85ba64a92cc8d6efefb3dcedaf1319355e3f3db1
|
||||
@ -38,7 +38,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
|
||||
-CC "-std=c++11" \
|
||||
-CC "-Wl,-rpath,$(RISCV)/lib" \
|
||||
-CC "-include $(consts_header)" \
|
||||
-CC "-include $(scr_header)" \
|
||||
-e vcs_main \
|
||||
$(RISCV)/lib/libfesvr.so \
|
||||
$(sim_dir)/libdramsim.a \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user