Purge legacy HTIF things

The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.

Makefrag

@@ -64,7 +64,6 @@ $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
 
 params_file = $(generated_dir)/$(MODEL).$(CONFIG).prm
 consts_header = $(generated_dir)/consts.$(CONFIG).h
-scr_header = $(generated_dir)/$(MODEL).$(CONFIG).scr_map.h
 $(consts_header): $(params_file)
 	echo "#ifndef __CONST_H__" > $@
 	echo "#define __CONST_H__" >> $@
@@ -80,4 +79,3 @@ $(consts_header_debug): $(params_file_debug)
 	sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/#define \1 \2/' $< >> $@
 	echo "#define TBFRAG \"$(MODEL).$(CONFIG).tb.cpp\"" >> $@
 	echo "#endif // __CONST_H__" >> $@
-scr_header_debug = $(generated_dir_debug)/$(MODEL).$(CONFIG).scr_map.h

README.md

@@ -81,13 +81,27 @@ Similarly, to generate VLSI-synthesizable verilog (output will be in `vsim/gener
     $ cd vsim
     $ make verilog
 
-### Updating To A Newer Version Of Chisel
 
-To grab a newer version of chisel:
+### Keeping Your Repo Up-to-Date
 
-    $ git submodule update --init
+If you are trying to keep your repo up to date with this github repo,
-    $ cd chisel
+you also need to keep the submodules and tools up to date.
+
+    $ # Get the newest versions of the files in this repo
     $ git pull origin master
+    $ # Make sure the submodules have the correct versions
+    $ git submodule update --init --recursive
+
+If riscv-tools version changes, you should recompile and install riscv-tools according to the directions in the [riscv-tools/README](https://github.com/riscv/riscv-tools/blob/master/README.md).
+
+    $ cd riscv-tools
+    $ ./build.sh
+
+If firrtl version changes and you are using Chisel3, you may need to clean and recompile:
+
+    $ cd firrtl
+    $ sbt clean
+    $ sbt assembly
 
 ## <a name="what"></a> What's in the Rocket chip generator repository?
 
@@ -101,11 +115,12 @@ at Berkeley, the ability to compose a subset of private and public
 sub-repositories on a per-chip basis is a killer feature of git
 submodule.
 
-So, which submodules are actually included in this chip's repository?
+### <a name="what_submodules"></a>The Submodules
+
 Here's a look at all the git submodules that are currently tracked in
 the rocket-chip repository:
 
-* **chisel**
+* **chisel2**
 ([https://github.com/ucb-bar/chisel](https://github.com/ucb-bar/chisel)):
 At Berkeley, we write RTL in Chisel. For those who are not familiar
 with Chisel, please go take a look at
@@ -117,6 +132,17 @@ and hence it was easiest to use submodule to track bleeding edge commits
 to Chisel, which contained a bunch of new features and bug fixes. As
 Chisel gets more stable, we will likely replace this submodule with an
 external dependency.
+* **chisel3**
+([https://github.com/ucb-bar/chisel3](https://github.com/ucb-bar/chisel3)):
+Chisel3 is a newer version of Chisel, which is based on FIRRTL. The Chisel
+code in this repository is generally compatible with both Chisel2 and Chisel3.
+The [chisel3/README](https://github.com/ucb-bar/chisel3/blob/master/README.md).gives 
+instructions on how to build your design with Chisel3 instead of Chisel2.
+* **firrtl**
+([https://github.com/ucb-bar/firrtl](https://github.com/ucb-bar/firrtl)):
+FIRRTL (Flexible Internal Representation for RTL) is the intermediate format
+which Chisel3 is based upon. The Chisel3 compiler generates a FIRRTL representation,
+from which the final product (Verilog code, C code, etc) is generated.
 * **rocket**
 ([https://github.com/ucb-bar/rocket](https://github.com/ucb-bar/rocket)):
 The rocket repository holds the actual source code of the Rocket core.
@@ -129,8 +155,12 @@ core within a memory system and connects it to the outside world.
 ([https://github.com/ucb-bar/uncore](https://github.com/ucb-bar/uncore)):
 This repository implements the uncore logic, such as the coherence hub
 (the agent that keeps multiple L1 D$ coherent). The definition of the
-coherent interfaces between tiles ("tilelink") and the interface to the
+coherent interfaces between tiles ("tilelink") and the debug interface
-host machine ("htif")  also live in this repository.
+also live in this repository.
+* **junctions**
+([https://github.com/ucb-bar/junctions](https://github.com/ucb-bar/junctions)):
+This repository contains code and
+converters for various bus protocols and interfaces. 
 * **hardfloat**
 ([https://github.com/ucb-bar/berkeley-hardfloat](https://github.com/ucb-bar/berkeley-hardfloat)):
 This repository holds the parameterized IEEE 754-2008 compliant
@@ -142,6 +172,12 @@ has an additional bit) to handle subnormal numbers more efficiently in
 the processor. Please take a look at the
 [README](https://github.com/ucb-bar/berkeley-hardfloat/blob/master/README.md)
 in the repository for more information.
+* **context-dependent-environments**
+([https://github.com/ucb-bar/context-dependent-environments](https://github.com/ucb-bar/context-dependent-environments)):
+The rocket-chip Chisel code is highly parameterizable, and utilizes the classes in 
+this subrepo to set and pass parameters to different levels of the design. Note that in 
+Chisel2, this was handled by Chisel itself, but has been moved into a seperate
+library for use with Chisel3. 
 * **dramsim2**
 ([https://github.com/dramninjasUMD/DRAMSim2](https://github.com/dramninjasUMD/DRAMSim2)):
 Currently, the DRAM memory system is implemented in the testbench. We
@@ -155,9 +191,22 @@ committed in the rocket-chip repository.
 We tag a version of riscv-tools that works with the RTL committed in the
 rocket-chip repository.  Once the software toolchain stabilizes, we
 might turn this submodule into an external dependency.
+* **groundtest**
+([https://github.com/ucb-bar/groundtest](https://github.com/ucb-bar/groundtest)):
+This repository contains code which can test the uncore by generating randomized
+instruction streams. It replaces the rocket processor with an instruction
+stream generator to stress-test the uncore portions of the design.
+* **torture**
+([https://github.com/ucb-bar/torture](https://github.com/ucb-bar/torture)):
+The torture test code is used to generate randomized instruction streams which
+are then run as code on the rocket core(s). These are constrained random tests
+to stress-test both the core and uncore portions of the design.
 
-Next, take a look at rocket-chip's src/main/scala directory. There are a
+### <a name="what_toplevel"></a>The Submodules
-couple Chisel source files including RocketChip.scala, which
+
+Next, take a look at rocket-chip's src/main/scala directory.
+This directory has the Chisel source files including the top level
+RocketChip.scala, which
 instantiates both a Rocket core and the uncore logic, and then glues
 them together. Here's a brief overview of source files found in the
 rocket-chip repository:
@@ -184,37 +233,46 @@ down to Verilog. Pretty neat huh?
 implements logic to interface with an arbitrary number of slow
 single-ended digital I/Os when implementing a test chip.
 
-Now you should take a look at the top-level I/O pins. Open up
+Take a look at the top-level I/O pins. Open up
 src/main/scala/RocketChip.scala, and search for TopIO. You will read the
-following (note, HostIO is defined in uncore/src/main/scala/htif.scala,
+following:
-and MemIO is defined in uncore/src/main/scala/memserdes.scala):
 
-    class TopIO extends Bundle {
+    /** Top-level io for the chip */
-      val host    = new HostIO
+    class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
-      val mem     = new MemIO
+        with HasTopLevelParameters
-      val mem_backup_en = Bool(INPUT)
+
-      val in_mem_ready = Bool(OUTPUT)
+    class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
-      val in_mem_valid = Bool(INPUT)
+
-      val out_mem_ready = Bool(INPUT)
+      val mem_axi = Vec(nMemAXIChannels, new NastiIO)
-      val out_mem_valid = Bool(OUTPUT)
+      val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
+      val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
+      val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
+      val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
+      val debug = new DebugBusIO()(p).flip
     }
 
-There are 3 major I/O ports coming out of the top-level module:
+    
+There are 5 major I/O ports coming out of the top-level module:
 
-* **Host-target interface (HostIO)**: The host system talks to the
+* **Host-target interface (host)**: The host system talks to the
 target machine via this host-target interface. We serialize a simple
-protocol over this parameterized interface. More details will come.
+protocol over this parameterized interface. This interface is slated
-* **High-performance memory interface (MemIO, mem\_backup\_en=false)**:
+for removal in the near future.
-When mem\_backup\_en is tied low, all memory requests from the processor
+* **Debug interface (debug)**:
-comes out the MemIO port. The MemIO port uses the same uncore clock, and
+The debug interface can be used to both debug the processor as
+it is executing, and to read and write memory. It is slated to repalce the
+host interface in the near future.
+* **High-performance memory interface (mem_*) **:
+Memory requests from the processor comes out the mem_* ports.
+Depending on the configuration of the design, these may be visible as
+AXI or AHB protocol. The mem_* port(s) uses the same uncore clock, and
 is intended to be connected to something on the same chip.
-* **Low-performance memory interface (parts of HostIO, in\_mem\_\*,
+* ** Memory mapped I/O interface (mmio_*) **:
-out\_mem\_\*, mem\_backup\_en=true)**: When mem\_backup\_en is tied
+The optional mmio_* interfaces can be used to communicate with devices
-high, all memory requests from the processor comes out the
+on the chip but outside of the rocket-chip boundary. Depending on the
-low-performance memory interface. To save actual pins on a test chip, we
+configuration of the design, these may be visible as AXI or AHB.
-multiplex the data pins of the host-target interface with the serialized
+* ** Interrupts interface (interrupts) **: This interface is used to
-low-performance memory port. That's the reason why you only see the
+deliver external interrupts to the processor core.
-control pins (in\_mem\_* and out\_mem\_*).
 
 Of course, there's a lot more in the actual submodules, but hopefully
 this would be enough to get you started with using the Rocket chip
@@ -227,7 +285,7 @@ list.
 
 Chisel can generate code for three targets: a high-performance
 cycle-accurate C++ emulator, Verilog optimized for FPGAs, and Verilog
-for VLSI. The Rocket chip generator can target all three backends.  You
+for VLSI. The rocket-chip generator can target all three backends.  You
 will need a Java runtime installed on your machine, since Chisel is
 overlaid on top of [Scala](http://www.scala-lang.org/). Chisel RTL (i.e.
 rocket-chip source code) is a Scala program executing on top of your
@@ -314,7 +372,7 @@ emulator/output/rv64ui-p-add.out:
     C0: 484 [1] pc=[0000000213c] W[r29=000000007fff8000][1] R[r31=ffffffff80007ffe] R[r31=0000000000000005] inst=[7fff8eb7] lui t3, 0x7fff8
     C0: 485 [0] pc=[00000002140] W[r 0=0000000000000000][0] R[r 0=0000000000000000] R[r 0=0000000000000000] inst=[00000000] unknown
 
-This means at cycle 483, core 0, the first [1] shows that there's a
+The first [1] at cycle 483, core 0, shows that there's a
 valid instruction at PC 0x2138 in the writeback stage, which is
 0x002081b3 (add s1, ra, s0). The second [1] tells us that the register
 file is writing r3 with the corresponding value 0x7fff7fff. When the add
@@ -443,6 +501,18 @@ This parameterization is one of the many strengths of processor
 generators written in Chisel, and will be more detailed in a future blog
 post, so please stay tuned.
 
+To override specific configuration items, such as the number of external interrupts,
+you can create your own Configuration(s) and compose them with Config's ++ operator
+
+    class WithNExtInterrupts extends Config (nExt: Int) {
+      (pname, site, here) => pname match {
+      case (NExtInterrupts => nExt)
+      }
+    } 
+    class MyConfig extends Config (new WithNExtInterrupts(16) ++ new DefaultSmallConfig)
+
+Then you can build as usual with CONFIG=MyConfig.
+
 ## <a name="contributors"></a> Contributors
 
 - Scott Beamer

csrc/htif_emulator.h

@@ -1,39 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _HTIF_EMULATOR_H
-#define _HTIF_EMULATOR_H
-
-#include <fesvr/htif_pthread.h>
-
-class htif_emulator_t : public htif_pthread_t
-{
- int memory_channel_mux_select;
-
- public:
-  htif_emulator_t(const std::vector<std::string>& args)
-    : htif_pthread_t(args),
-      memory_channel_mux_select(0)
-  {
-    for (const auto& arg: args) {
-      if (!strncmp(arg.c_str(), "+memory_channel_mux_select=", 27))
-        memory_channel_mux_select = atoi(arg.c_str()+27);
-    }
- }
-
-  void set_clock_divisor(int divisor, int hold_cycles)
-  {
-#ifdef UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR__OFFSET
-    /* We only want to write the HTIF clock divisor SCR on targets where it
-     * actually exists (there isn't one on the FPGA, for example). */
-    write_cr(-1, UNCORE_SCR__HTIF_IO_CLOCK_DIVISOR__OFFSET, divisor | hold_cycles << 16);
-#endif
-  }
-
-  void start()
-  {
-    set_clock_divisor(5, 2);
-    htif_pthread_t::start();
-  }
-};
-
-#endif

emulator/Makefrag-emulator

@@ -22,10 +22,10 @@ $(generated_dir_debug)/%.o: $(generated_dir_debug)/%.cpp $(generated_dir_debug)/
 	$(CXX) $(CXXFLAGS) -I$(generated_dir_debug) -c -o $@ $<
 
 $(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header) $(consts_header)
-	$(CXX) $(CXXFLAGS) -include $(scr_header) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
+	$(CXX) $(CXXFLAGS) -include $(model_header) -include $(consts_header) -I$(generated_dir) -c -o $@ $<
 
 $(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h $(model_header_debug) $(consts_header_debug)
-	$(CXX) $(CXXFLAGS) -include $(scr_header_debug) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<
+	$(CXX) $(CXXFLAGS) -include $(model_header_debug) -include $(consts_header_debug) -I$(generated_dir_debug) -c -o $@ $<
 
 $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.$(CONFIG).h $(generated_dir)/%.$(CONFIG).prm: $(chisel_srcs)
 	cd $(base_dir) && $(SBT) "project $(PROJECT)" "run $(CHISEL_ARGS) --noIoDebug"

emulator/Makefrag-verilator

@@ -69,12 +69,12 @@ $(emu): $(verilog) $(cppfiles) libdramsim.a $(consts_header) $(INSTALLED_VERILAT
 	mkdir -p $(generated_dir)/$(MODEL).$(CONFIG)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir)/$(MODEL).$(CONFIG) \
 	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-	-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header) -include $(scr_header)"
+	-CFLAGS "-I$(generated_dir) -include $(model_header) -include $(consts_header)"
 	$(MAKE) -C $(generated_dir)/$(MODEL).$(CONFIG) -f V$(MODEL).mk
 
 $(emu_debug): $(verilog_debug) $(cppfiles) libdramsim.a $(consts_header_debug) $(generated_dir)/$(MODEL).$(CONFIG).d $(INSTALLED_VERILATOR)
 	mkdir -p $(generated_dir_debug)/$(MODEL).$(CONFIG)
 	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(generated_dir_debug)/$(MODEL).$(CONFIG)  --trace \
 	-o $(abspath $(sim_dir))/$@ $< $(cppfiles) -LDFLAGS "$(LDFLAGS)" \
-	-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug) -include $(scr_header_debug)"
+	-CFLAGS "-I$(generated_dir_debug) -include $(model_header_debug) -include $(consts_header_debug)"
 	$(MAKE) -C $(generated_dir_debug)/$(MODEL).$(CONFIG) -f V$(MODEL).mk

fsim/Makefrag

@@ -39,7 +39,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	-CC "-std=c++11" \
 	-CC "-Wl,-rpath,$(RISCV)/lib" \
 	-CC "-include $(consts_header)" \
-	-CC "-include $(scr_header)" \
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \

src/main/scala/Configs.scala

@@ -108,12 +108,6 @@ class BaseConfig extends Config (
     lazy val innerDataBits = site(MIFDataBits)
     lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
     pname match {
-      case HtifKey => HtifParameters(
-                       width = Dump("HTIF_WIDTH", 16),
-                       nSCR = 64,
-                       csrDataBits = site(XLen),
-                       offsetBits = site(CacheBlockOffsetBits),
-                       nCores = site(NTiles))
       //Memory Parameters
       case PAddrBits => 32
       case PgIdxBits => 12
@@ -312,7 +306,6 @@ class BaseConfig extends Config (
       case BankIdLSB => 0
       case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
       case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
-      case UseHtifClockDiv => true
       case ConfigString => makeConfigString()
       case GlobalAddrMap => globalAddrMap
       case _ => throw new CDEMatchError
@@ -413,7 +406,6 @@ class WithRV32 extends Config(
 class FPGAConfig extends Config (
   (pname,site,here) => pname match {
     case NAcquireTransactors => 4
-    case UseHtifClockDiv => false
     case _ => throw new CDEMatchError
   }
 )

src/main/scala/RocketChip.scala

@@ -31,8 +31,6 @@ case object NOutstandingMemReqsPerChannel extends Field[Int]
 /** Number of exteral MMIO ports */
 case object NExtMMIOAXIChannels extends Field[Int]
 case object NExtMMIOAHBChannels extends Field[Int]
-/** Whether to divide HTIF clock */
-case object UseHtifClockDiv extends Field[Boolean]
 /** Function for building some kind of coherence manager agent */
 case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
 /** Function for building some kind of tile connected to a reset signal */
@@ -66,11 +64,6 @@ trait HasTopLevelParameters {
   lazy val mifAddrBits = p(MIFAddrBits)
   lazy val mifDataBeats = p(MIFDataBeats)
   lazy val xLen = p(XLen)
-  lazy val nSCR =  p(HtifKey).nSCR
-  lazy val scrAddrBits = log2Up(nSCR)
-  lazy val scrDataBits = 64
-  lazy val scrDataBytes = scrDataBits / 8
-  //require(lsb + log2Up(nBanks) < mifAddrBits)
 }
 
 class MemBackupCtrlIO extends Bundle {
@@ -176,7 +169,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
 /** Wrapper around everything that isn't a Tile.
   *
   * Usually this is clocked and/or place-and-routed separately from the Tiles.
-  * Contains the Host-Target InterFace module (HTIF).
   */
 class Uncore(implicit val p: Parameters) extends Module
     with HasTopLevelParameters {

src/main/scala/Testing.scala

@@ -5,7 +5,6 @@ package rocketchip
 import Chisel._
 import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
 import cde.{Parameters, ParameterDump, Config}
-import uncore.AllSCRFiles
 
 abstract class RocketTestSuite {
   val dir: String
@@ -201,7 +200,4 @@ object TestGenerator extends App with FileSystemUtilities {
   val w = createOutputFile(configClassName + ".cst")
   w.write(world.getConstraints)
   w.close
-  val scr_map_hdr = createOutputFile(topModuleName + "." + configClassName + ".scr_map.h")
-  AllSCRFiles.foreach{ map => scr_map_hdr.write(map.as_c_header) }
-  scr_map_hdr.close
 }

vsim/Makefrag

@@ -38,7 +38,6 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	-CC "-std=c++11" \
 	-CC "-Wl,-rpath,$(RISCV)/lib" \
 	-CC "-include $(consts_header)" \
-	-CC "-include $(scr_header)" \
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \