Merge pull request #1012 from freechipsproject/halt-and-catch-fire
Halt and Catch Fire
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commit
5662d1de0b
@ -11,7 +11,8 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import TLMessages._
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class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
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class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)
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with CanHaveErrors {
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val correctable = (cacheParams.tagECC.canCorrect || cacheParams.dataECC.canCorrect).option(Valid(UInt(width = paddrBits)))
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val uncorrectable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
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val bus = Valid(UInt(width = paddrBits))
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@ -41,9 +42,9 @@ class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i)))
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val wWords = io.req.bits.wdata.grouped(encBits * (wordBits / eccBits))
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val addr = io.req.bits.addr >> rowOffBits
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val dcache_data_arrays = Seq.fill(rowBytes / wordBytes) { SeqMem(nSets * refillCycles, Vec(nWays * (wordBits / eccBits), UInt(width = encBits))) }
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val rdata = for ((array, i) <- dcache_data_arrays zipWithIndex) yield {
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val valid = io.req.valid && (Bool(dcache_data_arrays.size == 1) || io.req.bits.wordMask(i))
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val data_arrays = Seq.fill(rowBytes / wordBytes) { SeqMem(nSets * refillCycles, Vec(nWays * (wordBits / eccBits), UInt(width = encBits))) }
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val rdata = for ((array, i) <- data_arrays zipWithIndex) yield {
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val valid = io.req.valid && (Bool(data_arrays.size == 1) || io.req.bits.wordMask(i))
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when (valid && io.req.bits.write) {
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val wData = wWords(i).grouped(encBits)
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array.write(addr, Vec((0 until nWays).flatMap(i => wData)), wMask)
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@ -78,7 +79,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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// tags
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val replacer = cacheParams.replacement
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val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8))
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val dcache_tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(metaArb.io.out.bits.data.getWidth))))
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val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(metaArb.io.out.bits.data.getWidth))))
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// data
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val data = Module(new DCacheDataArray)
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@ -188,9 +189,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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when (metaReq.valid && metaReq.bits.write) {
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val wdata = tECC.encode(metaReq.bits.data.asUInt)
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val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.toBools
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dcache_tag_array.write(metaIdx, Vec.fill(nWays)(wdata), wmask)
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tag_array.write(metaIdx, Vec.fill(nWays)(wdata), wmask)
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}
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val s1_meta = dcache_tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write)
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val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write)
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val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata))
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val s1_tag = s1_paddr >> untagBits
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val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt
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@ -36,7 +36,9 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
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val addr = UInt(width = vaddrBits)
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}
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class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
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class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
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with HasL1ICacheParameters
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with CanHaveErrors {
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val correctable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
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val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
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}
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@ -174,13 +176,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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v
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}
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val icache_tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits))))
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val tag_rdata = icache_tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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val tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits))))
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val tag_rdata = tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
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val accruedRefillError = Reg(Bool())
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val refillError = tl_out.d.bits.error || (refill_cnt > 0 && accruedRefillError)
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when (refill_done) {
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val enc_tag = tECC.encode(Cat(refillError, refill_tag))
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icache_tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
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tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
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}
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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@ -222,8 +224,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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assert(!(s1_valid || s1_slaveValid) || PopCount(s1_tag_hit zip s1_tag_disparity map { case (h, d) => h && !d }) <= 1)
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require(tl_out.d.bits.data.getWidth % wordBits == 0)
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val icache_data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = dECC.width(wordBits)))) }
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for ((data_array, i) <- icache_data_arrays zipWithIndex) {
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val data_arrays = Seq.fill(tl_out.d.bits.data.getWidth / wordBits) { SeqMem(nSets * refillCycles, Vec(nWays, UInt(width = dECC.width(wordBits)))) }
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for ((data_array, i) <- data_arrays zipWithIndex) {
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def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i
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def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
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val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr))
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@ -628,12 +628,12 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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val resp = Wire(Vec(rowWords, Bits(width = encRowBits)))
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val r_raddr = RegEnable(io.read.bits.addr, io.read.valid)
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for (i <- 0 until resp.size) {
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val nbdcache_data_array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
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val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
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when (wway_en.orR && io.write.valid && io.write.bits.wmask(i)) {
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val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
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nbdcache_data_array.write(waddr, data, wway_en.toBools)
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array.write(waddr, data, wway_en.toBools)
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}
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resp(i) := nbdcache_data_array.read(raddr, rway_en.orR && io.read.valid).asUInt
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resp(i) := array.read(raddr, rway_en.orR && io.read.valid).asUInt
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}
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for (dw <- 0 until rowWords) {
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val r = Vec(resp.map(_(encDataBits*(dw+1)-1,encDataBits*dw)))
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@ -645,12 +645,12 @@ class DataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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}
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} else {
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for (w <- 0 until nWays) {
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val nbdcache_data_array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
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val array = SeqMem(nSets*refillCycles, Vec(rowWords, Bits(width=encDataBits)))
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when (io.write.bits.way_en(w) && io.write.valid) {
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val data = Vec.tabulate(rowWords)(i => io.write.bits.data(encDataBits*(i+1)-1,encDataBits*i))
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nbdcache_data_array.write(waddr, data, io.write.bits.wmask.toBools)
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array.write(waddr, data, io.write.bits.wmask.toBools)
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}
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io.resp(w) := nbdcache_data_array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt
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io.resp(w) := array.read(raddr, io.read.bits.way_en(w) && io.read.valid).asUInt
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}
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}
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@ -20,6 +20,7 @@ case class RocketTileParams(
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dataScratchpadBytes: Int = 0,
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boundaryBuffers: Boolean = false,
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trace: Boolean = false,
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hcfOnUncorrectable: Boolean = false,
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name: Option[String] = Some("tile"),
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externalMasterBuffers: Int = 0,
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externalSlaveBuffers: Int = 0) extends TileParams {
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@ -131,6 +132,9 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
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class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
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with HasExternalInterruptsBundle
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with CanHaveScratchpadBundle
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with CanHaltAndCatchFire {
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val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(Bool(OUTPUT))
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}
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class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => new RocketTileBundle(outer))
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with HasExternalInterruptsModule
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@ -138,9 +142,12 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
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with CanHaveScratchpadModule {
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val core = Module(p(BuildCore)(outer.p))
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val uncorrectable = RegInit(Bool(false))
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decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
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core.io.hartid := io.hartid // Pass through the hartid
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io.trace.foreach { _ := core.io.trace }
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io.halt_and_catch_fire.foreach { _ := uncorrectable }
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outer.frontend.module.io.cpu <> core.io.imem
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outer.frontend.module.io.reset_vector := io.reset_vector
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outer.frontend.module.io.hartid := io.hartid
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@ -154,6 +161,12 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
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core.io.rocc.busy := roccCore.busy
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core.io.rocc.interrupt := roccCore.interrupt
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when(!uncorrectable) { uncorrectable :=
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List(outer.frontend.module.io.errors, outer.dcache.module.io.errors)
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.flatMap { e => e.uncorrectable.map(_.valid) }
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.reduceOption(_||_)
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.getOrElse(false.B)
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}
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// TODO eliminate this redundancy
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val h = dcachePorts.size
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@ -207,18 +220,23 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
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}
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lazy val module = new LazyModuleImp(this) {
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val io = new CoreBundle with HasExternallyDrivenTileConstants with CanHaveInstructionTracePort {
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val io = new CoreBundle
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with HasExternallyDrivenTileConstants
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with CanHaveInstructionTracePort
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with CanHaltAndCatchFire {
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val master = masterNode.bundleOut
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val slave = slaveNode.bundleIn
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val outputInterrupts = intOutputNode.map(_.bundleOut)
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val asyncInterrupts = asyncIntNode.bundleIn
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val periphInterrupts = periphIntNode.bundleIn
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val coreInterrupts = coreIntNode.bundleIn
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val halt_and_catch_fire = rocket.module.io.halt_and_catch_fire.map(_.cloneType)
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}
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// signals that do not change based on crossing type:
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rocket.module.io.hartid := io.hartid
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rocket.module.io.reset_vector := io.reset_vector
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io.trace.foreach { _ := rocket.module.io.trace.get }
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io.halt_and_catch_fire.foreach { _ := rocket.module.io.halt_and_catch_fire.get }
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}
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}
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@ -173,3 +173,8 @@ class SECDEDTest extends Module
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io.correctable := d.correctable
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io.uncorrectable := d.uncorrectable
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}
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trait CanHaveErrors extends Bundle {
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val correctable: Option[ValidIO[UInt]]
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val uncorrectable: Option[ValidIO[UInt]]
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}
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@ -26,6 +26,10 @@ trait Clocked extends Bundle {
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val reset = Bool()
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}
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trait CanHaltAndCatchFire extends Bundle {
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val halt_and_catch_fire: Option[Bool]
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}
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object DecoupledHelper {
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def apply(rvs: Bool*) = new DecoupledHelper(rvs)
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}
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