riscv/rocket-chip
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Avoid need for FENCE.I in debug programs

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This is a hack to work around caching the (uncacheable) debug RAM.  The
RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR.
This commit is contained in:
Andrew Waterman 2016-06-22 13:49:33 -07:00
parent 7f88a00a38
commit 5644a2703a
1 changed files with 5 additions and 0 deletions
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5
rocket/src/main/scala/rocket.scala
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@ -306,6 +306,11 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush || csr.io.singleStep ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush || csr.io.singleStep
ex_reg_load_use := id_load_use ex_reg_load_use := id_load_use
when (id_ctrl.jalr && csr.io.status.debug) {
ex_reg_flush_pipe := true
ex_ctrl.fence_i := true
}
for (i <- 0 until id_raddr.size) { for (i <- 0 until id_raddr.size) {
val do_bypass = id_bypass_src(i).reduce(_||_) val do_bypass = id_bypass_src(i).reduce(_||_)
val bypass_src = PriorityEncoder(id_bypass_src(i)) val bypass_src = PriorityEncoder(id_bypass_src(i))