From 5644a2703a08a2f6e7d312322d766d8525c8eed6 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 22 Jun 2016 13:49:33 -0700 Subject: [PATCH] Avoid need for FENCE.I in debug programs This is a hack to work around caching the (uncacheable) debug RAM. The RAM is always entered with a JALR, so flush the I$ on any debug-mode JALR. --- rocket/src/main/scala/rocket.scala | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 8a60609c..12a99608 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -306,6 +306,11 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush || csr.io.singleStep ex_reg_load_use := id_load_use + when (id_ctrl.jalr && csr.io.status.debug) { + ex_reg_flush_pipe := true + ex_ctrl.fence_i := true + } + for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_||_) val bypass_src = PriorityEncoder(id_bypass_src(i))