riscv/rocket-chip
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maskrom: retain data for d channel is not ready

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This commit is contained in:
Yunsup Lee 2017-08-07 12:17:10 -07:00
parent aff028f8f0
commit 558fc7f293
1 changed files with 2 additions and 1 deletions
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3
src/main/scala/devices/tilelink/MaskROM.scala
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@ -49,6 +49,7 @@ class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
val d_full = RegInit(Bool(false))
val d_size = Reg(UInt())
val d_source = Reg(UInt())
val d_data = rom.io.q holdUnless RegNext(in.a.fire())
// Flow control
when (in.d.fire()) { d_full := Bool(false) }
@ -61,7 +62,7 @@ class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
d_source := in.a.bits.source
}
in.d.bits := edge.AccessAck(d_source, d_size, rom.io.q)
in.d.bits := edge.AccessAck(d_source, d_size, d_data)
// Tie off unused channels
in.b.valid := Bool(false)