diff --git a/src/main/scala/devices/tilelink/MaskROM.scala b/src/main/scala/devices/tilelink/MaskROM.scala
index cb187673..ce801a4e 100644
--- a/src/main/scala/devices/tilelink/MaskROM.scala
+++ b/src/main/scala/devices/tilelink/MaskROM.scala
@@ -49,6 +49,7 @@ class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
     val d_full = RegInit(Bool(false))
     val d_size = Reg(UInt())
     val d_source = Reg(UInt())
+    val d_data = rom.io.q holdUnless RegNext(in.a.fire())
 
     // Flow control
     when (in.d.fire()) { d_full := Bool(false) }
@@ -61,7 +62,7 @@ class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
       d_source := in.a.bits.source
     }
 
-    in.d.bits := edge.AccessAck(d_source, d_size, rom.io.q)
+    in.d.bits := edge.AccessAck(d_source, d_size, d_data)
 
     // Tie off unused channels
     in.b.valid := Bool(false)