maskrom: retain data for d channel is not ready
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@ -49,6 +49,7 @@ class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
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val d_full = RegInit(Bool(false))
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val d_size = Reg(UInt())
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val d_source = Reg(UInt())
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val d_data = rom.io.q holdUnless RegNext(in.a.fire())
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// Flow control
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when (in.d.fire()) { d_full := Bool(false) }
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@ -61,7 +62,7 @@ class TLMaskROM(c: MaskROMParams)(implicit p: Parameters) extends LazyModule {
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d_source := in.a.bits.source
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}
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in.d.bits := edge.AccessAck(d_source, d_size, rom.io.q)
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in.d.bits := edge.AccessAck(d_source, d_size, d_data)
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// Tie off unused channels
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in.b.valid := Bool(false)
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