riscv/rocket-chip
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Don't route PLIC interrupts through PRCI

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The PLIC is local to the Coreplex, and PRCI should not be.
This commit is contained in:
Andrew Waterman
2016-09-13 16:25:31 -07:00
parent 38b13da2f4
commit 5566bf1b13
5 changed files with 34 additions and 36 deletions
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8
src/main/scala/rocket/rocket.scala
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@ -143,7 +143,8 @@ object ImmGen {
class Rocket(implicit p: Parameters) extends CoreModule()(p) {
val io = new Bundle {
val prci = new PRCITileIO().flip
val interrupts = new TileInterrupts().asInput
val hartid = UInt(INPUT, xLen)
val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
val ptw = new DatapathPTWIO().flip
@ -514,7 +515,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
csr.io.exception := wb_reg_xcpt
csr.io.cause := wb_reg_cause
csr.io.retire := wb_valid
csr.io.prci <> io.prci
csr.io.interrupts := io.interrupts
csr.io.hartid := io.hartid
io.fpu.fcsr_rm := csr.io.fcsr_rm
csr.io.fcsr_flags := io.fpu.fcsr_flags
csr.io.rocc.interrupt <> io.rocc.interrupt
@ -681,7 +683,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
}
else {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.prci.id, csr.io.time(31,0), wb_valid, wb_reg_pc,
io.hartid, csr.io.time(31,0), wb_valid, wb_reg_pc,
Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),