From 5566bf1b13228df1aa1af202a6b0d005de3f2b5b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 13 Sep 2016 16:25:31 -0700 Subject: [PATCH] Don't route PLIC interrupts through PRCI The PLIC is local to the Coreplex, and PRCI should not be. --- src/main/scala/coreplex/Coreplex.scala | 19 ++++++++----------- src/main/scala/rocket/csr.scala | 17 +++++++++++++---- src/main/scala/rocket/rocket.scala | 8 +++++--- src/main/scala/rocket/tile.scala | 6 ++++-- src/main/scala/uncore/devices/Prci.scala | 20 ++++---------------- 5 files changed, 34 insertions(+), 36 deletions(-) diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index 70d1343b..cf2782bb 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -174,17 +174,14 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, prci.io.tl <> mmioNetwork.port("int:prci") prci.io.rtcTick := io.rtcTick - (prci.io.tiles, tileResets, tileList).zipped.foreach { - case (prci, rst, tile) => - rst := reset - tile.io.prci <> prci - } - - for (i <- 0 until tc.nTiles) { - prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M')) - if (p(UseVM)) - prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S')) - prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i) + // connect coreplex-internal interrupts to tiles + for (((tile, tileReset), i) <- (tileList zip tileResets) zipWithIndex) { + tileReset := prci.io.tiles(i).reset + tile.io.interrupts := prci.io.tiles(i).interrupts + tile.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M')) + tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S'))) + tile.io.interrupts.debug := debugModule.io.debugInterrupts(i) + tile.io.hartid := i } val tileSlavePorts = (0 until tc.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _) diff --git a/src/main/scala/rocket/csr.scala b/src/main/scala/rocket/csr.scala index e75edb47..8b3ecff0 100644 --- a/src/main/scala/rocket/csr.scala +++ b/src/main/scala/rocket/csr.scala @@ -61,6 +61,14 @@ class DCSR extends Bundle { val prv = UInt(width = PRV.SZ) } +class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) { + val debug = Bool() + val mtip = Bool() + val msip = Bool() + val meip = Bool() + val seip = usingVM.option(Bool()) +} + class MIP extends Bundle { val rocc = Bool() val meip = Bool() @@ -121,7 +129,8 @@ object CSR } class CSRFileIO(implicit p: Parameters) extends CoreBundle { - val prci = new PRCITileIO().flip + val interrupts = new TileInterrupts().asInput + val hartid = UInt(INPUT, xLen) val rw = new Bundle { val addr = UInt(INPUT, CSR.ADDRSZ) val cmd = Bits(INPUT, CSR.SZ) @@ -297,7 +306,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) CSRs.mepc -> reg_mepc.sextTo(xLen), CSRs.mbadaddr -> reg_mbadaddr.sextTo(xLen), CSRs.mcause -> reg_mcause, - CSRs.mhartid -> io.prci.id) + CSRs.mhartid -> io.hartid) val debug_csrs = collection.immutable.ListMap( CSRs.dcsr -> reg_dcsr.asUInt, @@ -611,8 +620,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p) } } - reg_mip := io.prci.interrupts - reg_dcsr.debugint := io.prci.interrupts.debug + reg_mip := io.interrupts + reg_dcsr.debugint := io.interrupts.debug reg_sptbr.asid := 0 if (nBreakpoints <= 1) reg_tselect := 0 diff --git a/src/main/scala/rocket/rocket.scala b/src/main/scala/rocket/rocket.scala index 6fa6893a..61b013b2 100644 --- a/src/main/scala/rocket/rocket.scala +++ b/src/main/scala/rocket/rocket.scala @@ -143,7 +143,8 @@ object ImmGen { class Rocket(implicit p: Parameters) extends CoreModule()(p) { val io = new Bundle { - val prci = new PRCITileIO().flip + val interrupts = new TileInterrupts().asInput + val hartid = UInt(INPUT, xLen) val imem = new FrontendIO()(p.alterPartial({case CacheName => "L1I" })) val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" })) val ptw = new DatapathPTWIO().flip @@ -514,7 +515,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { csr.io.exception := wb_reg_xcpt csr.io.cause := wb_reg_cause csr.io.retire := wb_valid - csr.io.prci <> io.prci + csr.io.interrupts := io.interrupts + csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm csr.io.fcsr_flags := io.fpu.fcsr_flags csr.io.rocc.interrupt <> io.rocc.interrupt @@ -681,7 +683,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) { } else { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", - io.prci.id, csr.io.time(31,0), wb_valid, wb_reg_pc, + io.hartid, csr.io.time(31,0), wb_valid, wb_reg_pc, Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen, wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))), wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))), diff --git a/src/main/scala/rocket/tile.scala b/src/main/scala/rocket/tile.scala index df055f90..1a868fa8 100644 --- a/src/main/scala/rocket/tile.scala +++ b/src/main/scala/rocket/tile.scala @@ -31,7 +31,8 @@ abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null) class TileIO extends Bundle { val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO) val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO) - val prci = new PRCITileIO().flip + val hartid = UInt(INPUT, p(XLen)) + val interrupts = new TileInterrupts().asInput val slave = (p(DataScratchpadSize) > 0).option(new ClientUncachedTileLinkIO().flip) } @@ -54,7 +55,8 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null) val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem) val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]() val cachedPorts = collection.mutable.ArrayBuffer(dcache.mem) - core.io.prci <> io.prci + core.io.interrupts := io.interrupts + core.io.hartid := io.hartid icache.io.cpu <> core.io.imem val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg))) diff --git a/src/main/scala/uncore/devices/Prci.scala b/src/main/scala/uncore/devices/Prci.scala index 24232fd8..d607be91 100644 --- a/src/main/scala/uncore/devices/Prci.scala +++ b/src/main/scala/uncore/devices/Prci.scala @@ -13,21 +13,11 @@ import cde.{Parameters, Field} /** Number of tiles */ case object NTiles extends Field[Int] -class PRCIInterrupts extends Bundle { - val meip = Bool() - val seip = Bool() - val debug = Bool() -} - class PRCITileIO(implicit p: Parameters) extends Bundle { val reset = Bool(OUTPUT) - val id = UInt(OUTPUT, log2Up(p(NTiles))) - val interrupts = { - val result = new PRCIInterrupts { - val mtip = Bool() - val msip = Bool() - } - result.asOutput + val interrupts = new Bundle { + val mtip = Bool() + val msip = Bool() } override def cloneType: this.type = new PRCITileIO().asInstanceOf[this.type] @@ -47,7 +37,6 @@ class PRCI(implicit val p: Parameters) extends Module with HasTileLinkParameters with HasAddrMapParameters { val io = new Bundle { - val interrupts = Vec(p(NTiles), new PRCIInterrupts).asInput val tl = new ClientUncachedTileLinkIO().flip val tiles = Vec(p(NTiles), new PRCITileIO) val rtcTick = Bool(INPUT) @@ -84,10 +73,9 @@ class PRCI(implicit val p: Parameters) extends Module } for ((tile, i) <- io.tiles zipWithIndex) { - tile.interrupts := io.interrupts(i) tile.interrupts.msip := ipi(i)(0) tile.interrupts.mtip := time >= timecmp(i) - tile.id := UInt(i) + tile.reset := reset } // TODO generalize these to help other TL slaves