riscv/rocket-chip
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Don't route PLIC interrupts through PRCI

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The PLIC is local to the Coreplex, and PRCI should not be.
This commit is contained in:
Andrew Waterman
2016-09-13 16:25:31 -07:00
parent 38b13da2f4
commit 5566bf1b13
5 changed files with 34 additions and 36 deletions
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17
src/main/scala/rocket/csr.scala
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@ -61,6 +61,14 @@ class DCSR extends Bundle {
val prv = UInt(width = PRV.SZ)
}
class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
val debug = Bool()
val mtip = Bool()
val msip = Bool()
val meip = Bool()
val seip = usingVM.option(Bool())
}
class MIP extends Bundle {
val rocc = Bool()
val meip = Bool()
@ -121,7 +129,8 @@ object CSR
}
class CSRFileIO(implicit p: Parameters) extends CoreBundle {
val prci = new PRCITileIO().flip
val interrupts = new TileInterrupts().asInput
val hartid = UInt(INPUT, xLen)
val rw = new Bundle {
val addr = UInt(INPUT, CSR.ADDRSZ)
val cmd = Bits(INPUT, CSR.SZ)
@ -297,7 +306,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
CSRs.mepc -> reg_mepc.sextTo(xLen),
CSRs.mbadaddr -> reg_mbadaddr.sextTo(xLen),
CSRs.mcause -> reg_mcause,
CSRs.mhartid -> io.prci.id)
CSRs.mhartid -> io.hartid)
val debug_csrs = collection.immutable.ListMap(
CSRs.dcsr -> reg_dcsr.asUInt,
@ -611,8 +620,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
}
}
reg_mip := io.prci.interrupts
reg_dcsr.debugint := io.prci.interrupts.debug
reg_mip := io.interrupts
reg_dcsr.debugint := io.interrupts.debug
reg_sptbr.asid := 0
if (nBreakpoints <= 1) reg_tselect := 0