Don't route PLIC interrupts through PRCI

The PLIC is local to the Coreplex, and PRCI should not be.

src/main/scala/rocket/csr.scala

@@ -61,6 +61,14 @@ class DCSR extends Bundle {
   val prv = UInt(width = PRV.SZ)
 }
 
+class TileInterrupts(implicit p: Parameters) extends CoreBundle()(p) {
+  val debug = Bool()
+  val mtip = Bool()
+  val msip = Bool()
+  val meip = Bool()
+  val seip = usingVM.option(Bool())
+}
+
 class MIP extends Bundle {
   val rocc = Bool()
   val meip = Bool()
@@ -121,7 +129,8 @@ object CSR
 }
 
 class CSRFileIO(implicit p: Parameters) extends CoreBundle {
-  val prci = new PRCITileIO().flip
+  val interrupts = new TileInterrupts().asInput
+  val hartid = UInt(INPUT, xLen)
   val rw = new Bundle {
     val addr = UInt(INPUT, CSR.ADDRSZ)
     val cmd = Bits(INPUT, CSR.SZ)
@@ -297,7 +306,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     CSRs.mepc -> reg_mepc.sextTo(xLen),
     CSRs.mbadaddr -> reg_mbadaddr.sextTo(xLen),
     CSRs.mcause -> reg_mcause,
-    CSRs.mhartid -> io.prci.id)
+    CSRs.mhartid -> io.hartid)
 
   val debug_csrs = collection.immutable.ListMap(
     CSRs.dcsr -> reg_dcsr.asUInt,
@@ -611,8 +620,8 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
     }
   }
 
-  reg_mip := io.prci.interrupts
-  reg_dcsr.debugint := io.prci.interrupts.debug
+  reg_mip := io.interrupts
+  reg_dcsr.debugint := io.interrupts.debug
 
   reg_sptbr.asid := 0
   if (nBreakpoints <= 1) reg_tselect := 0

src/main/scala/rocket/rocket.scala

@@ -143,7 +143,8 @@ object ImmGen {
 
 class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   val io = new Bundle {
-    val prci = new PRCITileIO().flip
+    val interrupts = new TileInterrupts().asInput
+    val hartid = UInt(INPUT, xLen)
     val imem  = new FrontendIO()(p.alterPartial({case CacheName => "L1I" }))
     val dmem = new HellaCacheIO()(p.alterPartial({ case CacheName => "L1D" }))
     val ptw = new DatapathPTWIO().flip
@@ -514,7 +515,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   csr.io.exception := wb_reg_xcpt
   csr.io.cause := wb_reg_cause
   csr.io.retire := wb_valid
-  csr.io.prci <> io.prci
+  csr.io.interrupts := io.interrupts
+  csr.io.hartid := io.hartid
   io.fpu.fcsr_rm := csr.io.fcsr_rm
   csr.io.fcsr_flags := io.fpu.fcsr_flags
   csr.io.rocc.interrupt <> io.rocc.interrupt
@@ -681,7 +683,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p) {
   }
   else {
     printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
-         io.prci.id, csr.io.time(31,0), wb_valid, wb_reg_pc,
+         io.hartid, csr.io.time(31,0), wb_valid, wb_reg_pc,
          Mux(rf_wen, rf_waddr, UInt(0)), rf_wdata, rf_wen,
          wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
          wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),

src/main/scala/rocket/tile.scala

@@ -31,7 +31,8 @@ abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
   class TileIO extends Bundle {
     val cached = Vec(nCachedTileLinkPorts, new ClientTileLinkIO)
     val uncached = Vec(nUncachedTileLinkPorts, new ClientUncachedTileLinkIO)
-    val prci = new PRCITileIO().flip
+    val hartid = UInt(INPUT, p(XLen))
+    val interrupts = new TileInterrupts().asInput
     val slave = (p(DataScratchpadSize) > 0).option(new ClientUncachedTileLinkIO().flip)
   }
 
@@ -54,7 +55,8 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
   val uncachedArbPorts = collection.mutable.ArrayBuffer(icache.io.mem)
   val uncachedPorts = collection.mutable.ArrayBuffer[ClientUncachedTileLinkIO]()
   val cachedPorts = collection.mutable.ArrayBuffer(dcache.mem)
-  core.io.prci <> io.prci
+  core.io.interrupts := io.interrupts
+  core.io.hartid := io.hartid
   icache.io.cpu <> core.io.imem
 
   val fpuOpt = p(FPUKey).map(cfg => Module(new FPU(cfg)))