riscv/rocket-chip
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Don't route PLIC interrupts through PRCI

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The PLIC is local to the Coreplex, and PRCI should not be.
This commit is contained in:
Andrew Waterman
2016-09-13 16:25:31 -07:00
parent 38b13da2f4
commit 5566bf1b13
5 changed files with 34 additions and 36 deletions
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19
src/main/scala/coreplex/Coreplex.scala
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@ -174,17 +174,14 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
prci.io.tl <> mmioNetwork.port("int:prci")
prci.io.rtcTick := io.rtcTick
(prci.io.tiles, tileResets, tileList).zipped.foreach {
case (prci, rst, tile) =>
rst := reset
tile.io.prci <> prci
}
for (i <- 0 until tc.nTiles) {
prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
if (p(UseVM))
prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
// connect coreplex-internal interrupts to tiles
for (((tile, tileReset), i) <- (tileList zip tileResets) zipWithIndex) {
tileReset := prci.io.tiles(i).reset
tile.io.interrupts := prci.io.tiles(i).interrupts
tile.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
tile.io.interrupts.debug := debugModule.io.debugInterrupts(i)
tile.io.hartid := i
}
val tileSlavePorts = (0 until tc.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)