riscv/rocket-chip
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add groundtest submodule for simple memory testing

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This commit is contained in:
Howard Mao 2015-11-10 13:39:08 -08:00
parent 149480411e
commit 55581195eb
5 changed files with 49 additions and 10 deletions
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3
.gitmodules vendored
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@ -28,3 +28,6 @@
[submodule "context-dependent-environments"] [submodule "context-dependent-environments"]
path = context-dependent-environments path = context-dependent-environments
url = https://github.com/ucb-bar/context-dependent-environments url = https://github.com/ucb-bar/context-dependent-environments
[submodule "groundtest"]
path = groundtest
url = https://github.com/ucb-bar/groundtest.git

2
Makefrag
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@ -14,7 +14,7 @@ SHELL := /bin/bash
CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir) CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
src_path = src/main/scala src_path = src/main/scala
default_submodules = . junctions uncore hardfloat rocket zscale default_submodules = . junctions uncore hardfloat rocket zscale groundtest
chisel_srcs = $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules) $(ROCKETCHIP_ADDONS))) chisel_srcs = $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules) $(ROCKETCHIP_ADDONS)))
disasm := 2> disasm := 2>

1
groundtest Submodule

@ -0,0 +1 @@
Subproject commit 5ed7616fef03d3291123a4844565a165d2738bf8

3
project/build.scala
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@ -22,7 +22,8 @@ object BuildSettings extends Build {
lazy val uncore = project.dependsOn(junctions) lazy val uncore = project.dependsOn(junctions)
lazy val rocket = project.dependsOn(hardfloat, uncore) lazy val rocket = project.dependsOn(hardfloat, uncore)
lazy val zscale = project.dependsOn(rocket) lazy val zscale = project.dependsOn(rocket)
lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale) lazy val groundtest = project.dependsOn(rocket)
lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale, groundtest)
lazy val addons = settingKey[Seq[String]]("list of addons used for this build") lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
lazy val make = inputKey[Unit]("trigger backend-specific makefile command") lazy val make = inputKey[Unit]("trigger backend-specific makefile command")

36
src/main/scala/Configs.scala
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@ -8,6 +8,7 @@ import uncore._
import rocket._ import rocket._
import rocket.Util._ import rocket.Util._
import zscale._ import zscale._
import groundtest._
import scala.math.max import scala.math.max
import DefaultTestSuites._ import DefaultTestSuites._
import cde.{Parameters, Config, Dump, Knob} import cde.{Parameters, Config, Dump, Knob}
@ -209,7 +210,7 @@ class WithL2Cache extends Config(
case NWays => Knob("L2_WAYS") case NWays => Knob("L2_WAYS")
case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
}: PartialFunction[Any,Any] }: PartialFunction[Any,Any]
case NAcquireTransactors => 2 case NAcquireTransactors => 3
case NSecondaryMisses => 4 case NSecondaryMisses => 4
case L2DirectoryRepresentation => new FullRepresentation(site(NTiles)) case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
case BuildL2CoherenceManager => (p: Parameters) => case BuildL2CoherenceManager => (p: Parameters) =>
@ -247,6 +248,39 @@ class WithZscale extends Config(
class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig) class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
class WithMemtest extends Config (
(pname, site, here) => pname match {
case TLKey("L1toL2") =>
TileLinkParameters(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
nCachingClients = site(NGeneratorTiles),
nCachelessClients = site(NGeneratorTiles) + 1,
maxClientXacts = 1,
maxClientsPerPort = site(NGeneratorsPerTile),
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8)
case NTiles => site(NGeneratorTiles)
case NGeneratorTiles => 2
case NGeneratorsPerTile => 1
case GenerateUncached => true
case GenerateCached => true
case MaxGenerateRequests => 8192
case BuildTiles => {
(0 until site(NTiles)).map { i =>
(r: Bool, p: Parameters) => Module(
new GeneratorTile(i, r)
(p.alterPartial({case TLId => "L1toL2"})))
}
}
})
class MemtestConfig extends Config(new WithMemtest ++ new DefaultConfig)
class MemtestL2Config extends Config(new WithMemtest ++ new DefaultL2Config)
class FPGAConfig extends Config ( class FPGAConfig extends Config (
(pname,site,here) => pname match { (pname,site,here) => pname match {
case NAcquireTransactors => 4 case NAcquireTransactors => 4