From 55581195eb51250888787f5ee8addae81ccbb67e Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 10 Nov 2015 13:39:08 -0800
Subject: [PATCH] add groundtest submodule for simple memory testing

---
 .gitmodules                  |  3 +++
 Makefrag                     |  2 +-
 groundtest                   |  1 +
 project/build.scala          | 17 +++++++++--------
 src/main/scala/Configs.scala | 36 +++++++++++++++++++++++++++++++++++-
 5 files changed, 49 insertions(+), 10 deletions(-)
 create mode 160000 groundtest

diff --git a/.gitmodules b/.gitmodules
index d46c03e4..0ea3dbc0 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -28,3 +28,6 @@
 [submodule "context-dependent-environments"]
 	path = context-dependent-environments
 	url = https://github.com/ucb-bar/context-dependent-environments
+[submodule "groundtest"]
+	path = groundtest
+	url = https://github.com/ucb-bar/groundtest.git
diff --git a/Makefrag b/Makefrag
index cb3f6b3d..e50278e1 100644
--- a/Makefrag
+++ b/Makefrag
@@ -14,7 +14,7 @@ SHELL := /bin/bash
 CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
 
 src_path = src/main/scala
-default_submodules = . junctions uncore hardfloat rocket zscale
+default_submodules = . junctions uncore hardfloat rocket zscale groundtest
 chisel_srcs = $(addprefix $(base_dir)/,$(addsuffix /$(src_path)/*.scala,$(default_submodules) $(ROCKETCHIP_ADDONS)))
 
 disasm := 2>
diff --git a/groundtest b/groundtest
new file mode 160000
index 00000000..5ed7616f
--- /dev/null
+++ b/groundtest
@@ -0,0 +1 @@
+Subproject commit 5ed7616fef03d3291123a4844565a165d2738bf8
diff --git a/project/build.scala b/project/build.scala
index af11ca2a..bab8afbc 100644
--- a/project/build.scala
+++ b/project/build.scala
@@ -15,14 +15,15 @@ object BuildSettings extends Build {
     libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value)
   )
 
-  lazy val chisel    = project
-  lazy val cde       = project in file("context-dependent-environments")
-  lazy val hardfloat = project.dependsOn(chisel)
-  lazy val junctions = project.dependsOn(chisel, cde)
-  lazy val uncore    = project.dependsOn(junctions)
-  lazy val rocket    = project.dependsOn(hardfloat, uncore)
-  lazy val zscale    = project.dependsOn(rocket)
-  lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale)
+  lazy val chisel     = project
+  lazy val cde        = project in file("context-dependent-environments")
+  lazy val hardfloat  = project.dependsOn(chisel)
+  lazy val junctions  = project.dependsOn(chisel, cde)
+  lazy val uncore     = project.dependsOn(junctions)
+  lazy val rocket     = project.dependsOn(hardfloat, uncore)
+  lazy val zscale     = project.dependsOn(rocket)
+  lazy val groundtest = project.dependsOn(rocket)
+  lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale, groundtest)
 
   lazy val addons = settingKey[Seq[String]]("list of addons used for this build")
   lazy val make = inputKey[Unit]("trigger backend-specific makefile command")
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 5e63b051..34934d6a 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -8,6 +8,7 @@ import uncore._
 import rocket._
 import rocket.Util._
 import zscale._
+import groundtest._
 import scala.math.max
 import DefaultTestSuites._
 import cde.{Parameters, Config, Dump, Knob}
@@ -209,7 +210,7 @@ class WithL2Cache extends Config(
       case NWays => Knob("L2_WAYS")
       case RowBits => site(TLKey(site(TLId))).dataBitsPerBeat
     }: PartialFunction[Any,Any] 
-    case NAcquireTransactors => 2
+    case NAcquireTransactors => 3
     case NSecondaryMisses => 4
     case L2DirectoryRepresentation => new FullRepresentation(site(NTiles))
     case BuildL2CoherenceManager => (p: Parameters) =>
@@ -247,6 +248,39 @@ class WithZscale extends Config(
 
 class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
 
+class WithMemtest extends Config (
+  (pname, site, here) => pname match {
+    case TLKey("L1toL2") => 
+      TileLinkParameters(
+        coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
+        nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
+        nCachingClients = site(NGeneratorTiles),
+        nCachelessClients = site(NGeneratorTiles) + 1,
+        maxClientXacts = 1,
+        maxClientsPerPort = site(NGeneratorsPerTile),
+        maxManagerXacts = site(NAcquireTransactors) + 2,
+        dataBits = site(CacheBlockBytes)*8)
+
+    case NTiles => site(NGeneratorTiles)
+
+    case NGeneratorTiles => 2
+    case NGeneratorsPerTile => 1
+    case GenerateUncached => true
+    case GenerateCached => true
+    case MaxGenerateRequests => 8192
+
+    case BuildTiles => {
+      (0 until site(NTiles)).map { i =>
+        (r: Bool, p: Parameters) => Module(
+          new GeneratorTile(i, r)
+            (p.alterPartial({case TLId => "L1toL2"})))
+      }
+    }
+  })
+
+class MemtestConfig extends Config(new WithMemtest ++ new DefaultConfig)
+class MemtestL2Config extends Config(new WithMemtest ++ new DefaultL2Config)
+
 class FPGAConfig extends Config (
   (pname,site,here) => pname match {
     case NAcquireTransactors => 4