riscv/rocket-chip
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tims: explictly name them for generated address map

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This commit is contained in:
Henry Cook 2017-06-16 12:55:59 -07:00
parent 6b79842e66
commit 5552f23294
3 changed files with 5 additions and 4 deletions
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2
src/main/scala/rocket/ICache.scala
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@ -40,11 +40,13 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
val device = new SimpleDevice("itim", Nil)
val slaveNode = icacheParams.itimAddr.map { itimAddr =>
val wordBytes = icacheParams.fetchBytes
TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = Seq(AddressSet(itimAddr, size-1)),
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
supportsPutFull = TransferSizes(1, wordBytes),

2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -15,7 +15,7 @@ import util._
class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
with HasCoreParameters {
val device = new MemoryDevice
val device = new SimpleDevice("dtim", Nil)
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),

5
src/main/scala/uncore/tilelink2/SRAM.scala
View File

@ -8,10 +8,9 @@ import config._
import diplomacy._
import util._
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val device = new MemoryDevice
val device = name.map(new SimpleDevice(_, Nil)).getOrElse(new MemoryDevice)
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),