From 5552f2329425f771f9c916295b03346bbf2ba7e1 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 16 Jun 2017 12:55:59 -0700 Subject: [PATCH] tims: explictly name them for generated address map --- src/main/scala/rocket/ICache.scala | 2 ++ src/main/scala/rocket/ScratchpadSlavePort.scala | 2 +- src/main/scala/uncore/tilelink2/SRAM.scala | 5 ++--- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index b4bb7aa2..cd4bed4d 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -40,11 +40,13 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache")) val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes + val device = new SimpleDevice("itim", Nil) val slaveNode = icacheParams.itimAddr.map { itimAddr => val wordBytes = icacheParams.fetchBytes TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = Seq(AddressSet(itimAddr, size-1)), + resources = device.reg, regionType = RegionType.UNCACHED, executable = true, supportsPutFull = TransferSizes(1, wordBytes), diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index df9312df..f2681fb2 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -15,7 +15,7 @@ import util._ class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule with HasCoreParameters { - val device = new MemoryDevice + val device = new SimpleDevice("dtim", Nil) val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = List(address), diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala index e4b3e43b..05cea3b8 100644 --- a/src/main/scala/uncore/tilelink2/SRAM.scala +++ b/src/main/scala/uncore/tilelink2/SRAM.scala @@ -8,10 +8,9 @@ import config._ import diplomacy._ import util._ -class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule +class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule { - val device = new MemoryDevice - + val device = name.map(new SimpleDevice(_, Nil)).getOrElse(new MemoryDevice) val node = TLManagerNode(Seq(TLManagerPortParameters( Seq(TLManagerParameters( address = List(address),