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tims: explictly name them for generated address map

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Henry Cook
2017-06-16 12:55:59 -07:00
parent 6b79842e66
commit 5552f23294
3 changed files with 5 additions and 4 deletions
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5
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -8,10 +8,9 @@ import config._
import diplomacy._
import util._
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val device = new MemoryDevice
val device = name.map(new SimpleDevice(_, Nil)).getOrElse(new MemoryDevice)
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),