tims: explictly name them for generated address map

src/main/scala/uncore/tilelink2/SRAM.scala

@@ -8,10 +8,9 @@ import config._
 import diplomacy._
 import util._
 
-class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
+class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4, name: Option[String] = None)(implicit p: Parameters) extends LazyModule
 {
-  val device = new MemoryDevice
-
+  val device = name.map(new SimpleDevice(_, Nil)).getOrElse(new MemoryDevice)
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = List(address),