riscv/rocket-chip
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tims: explictly name them for generated address map

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This commit is contained in:
Henry Cook
2017-06-16 12:55:59 -07:00
parent 6b79842e66
commit 5552f23294
3 changed files with 5 additions and 4 deletions
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2
src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -15,7 +15,7 @@ import util._
class ScratchpadSlavePort(address: AddressSet)(implicit p: Parameters) extends LazyModule
with HasCoreParameters {
val device = new MemoryDevice
val device = new SimpleDevice("dtim", Nil)
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = List(address),