riscv/rocket-chip
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tims: explictly name them for generated address map

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This commit is contained in:
Henry Cook
2017-06-16 12:55:59 -07:00
parent 6b79842e66
commit 5552f23294
3 changed files with 5 additions and 4 deletions
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2
src/main/scala/rocket/ICache.scala
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@ -40,11 +40,13 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame
val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
val device = new SimpleDevice("itim", Nil)
val slaveNode = icacheParams.itimAddr.map { itimAddr =>
val wordBytes = icacheParams.fetchBytes
TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = Seq(AddressSet(itimAddr, size-1)),
resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
supportsPutFull = TransferSizes(1, wordBytes),