riscv/rocket-chip
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bugfix for WB data buffer

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This commit is contained in:
Henry Cook 2016-03-31 15:26:39 -07:00
parent 1792d01ce1
commit 54dd82ff76
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/nbdcache.scala
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@ -583,7 +583,7 @@ class WritebackUnit(implicit p: Parameters) extends L1HellaCacheModule()(p) {
// then buffer enough data_resps to make a whole beat // then buffer enough data_resps to make a whole beat
val data_buf = Reg(Bits()) val data_buf = Reg(Bits())
when(active && r2_data_req_fired && !beat_done) { when(active && r2_data_req_fired && !beat_done) {
data_buf := Cat(io.data_resp, data_buf((refillCyclesPerBeat-1)*encRowBits-1, encRowBits)) data_buf := Cat(io.data_resp, data_buf((refillCyclesPerBeat)*encRowBits-1, encRowBits))
buf_v := (if(refillCyclesPerBeat > 2) buf_v := (if(refillCyclesPerBeat > 2)
Cat(UInt(1), buf_v(refillCyclesPerBeat-2,1)) Cat(UInt(1), buf_v(refillCyclesPerBeat-2,1))
else UInt(1)) else UInt(1))