riscv/rocket-chip
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Chisel3 compatibility: use >>Int instead of >>UInt

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This commit is contained in:
Andrew Waterman
2015-08-05 15:28:31 -07:00
parent fb5524372d
commit 546205b174
6 changed files with 9 additions and 9 deletions
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rocket/src/main/scala/rocket.scala
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@ -331,7 +331,7 @@ class Rocket extends CoreModule
// writeback arbitration
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
val dmem_resp_fpu = io.dmem.resp.bits.tag(0).toBool
val dmem_resp_waddr = io.dmem.resp.bits.tag.toUInt >> UInt(1)
val dmem_resp_waddr = io.dmem.resp.bits.tag.toUInt()(5,1)
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data