diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index b2a8482f..01d592a5 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -43,12 +43,12 @@ class HellaCacheArbiter(n: Int) extends Module io.requestor(i).xcpt := io.mem.xcpt io.requestor(i).ordered := io.mem.ordered resp.bits := io.mem.resp.bits - resp.bits.tag := io.mem.resp.bits.tag >> UInt(log2Up(n)) + resp.bits.tag := io.mem.resp.bits.tag >> log2Up(n) resp.bits.nack := io.mem.resp.bits.nack && tag_hit resp.bits.replay := io.mem.resp.bits.replay && tag_hit io.requestor(i).replay_next.valid := io.mem.replay_next.valid && io.mem.replay_next.bits(log2Up(n)-1,0) === UInt(i) - io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n)) + io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> log2Up(n) } } diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala index aba5d61b..3b5810b8 100644 --- a/rocket/src/main/scala/fpu.scala +++ b/rocket/src/main/scala/fpu.scala @@ -215,7 +215,7 @@ class FPToInt extends Module dcmp.io.a := in.in1 dcmp.io.b := in.in2 val dcmp_out = (~in.rm & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR - val dcmp_exc = (~in.rm & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UInt(4) + val dcmp_exc = (~in.rm & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << 4 val d2i = hardfloat.recodedFloatNToAny(in.in1, in.rm, in.typ ^ 1, 52, 12, 64) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 18e55b86..50294282 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -95,7 +95,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule io.ptw <> tlb.io.ptw tlb.io.req.valid := !stall && !icmiss - tlb.io.req.bits.vpn := s1_pc >> UInt(pgIdxBits) + tlb.io.req.bits.vpn := s1_pc >> pgIdxBits tlb.io.req.bits.asid := UInt(0) tlb.io.req.bits.passthrough := Bool(false) tlb.io.req.bits.instruction := Bool(true) @@ -257,7 +257,7 @@ class ICache extends FrontendModule // output signals io.resp.valid := s2_hit io.mem.acquire.valid := (state === s_request) - io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> UInt(blockOffBits)) + io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> blockOffBits) // control state machine switch (state) { diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index ac48b7b3..f58cc29e 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -332,7 +332,7 @@ class MSHRFile extends L1HellaCacheModule { idxMatch(i) := mshr.io.idx_match tagList(i) := mshr.io.tag - wbTagList(i) := mshr.io.wb_req.bits.addr_block >> UInt(idxBits) + wbTagList(i) := mshr.io.wb_req.bits.addr_block >> idxBits alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy mshr.io.req_pri_val := alloc_arb.io.in(i).ready @@ -437,7 +437,7 @@ class WritebackUnit extends L1HellaCacheModule { // We reissue the meta read as it sets up the mux ctrl for s2_data_muxed io.meta_read.valid := fire io.meta_read.bits.idx := req_idx - io.meta_read.bits.tag := req.addr_block >> UInt(idxBits) + io.meta_read.bits.tag := req.addr_block >> idxBits io.data_req.valid := fire io.data_req.bits.way_en := req.way_en diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index 0346f843..1b08ce87 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -125,7 +125,7 @@ class PTW(n: Int) extends CoreModule val resp_err = state === s_error val resp_val = state === s_done || resp_err - val r_resp_ppn = io.mem.req.bits.addr >> UInt(pgIdxBits) + val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count) for (i <- 0 until io.requestor.size) { diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala index 36d140a7..25df6265 100644 --- a/rocket/src/main/scala/rocket.scala +++ b/rocket/src/main/scala/rocket.scala @@ -331,7 +331,7 @@ class Rocket extends CoreModule // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).toBool - val dmem_resp_waddr = io.dmem.resp.bits.tag.toUInt >> UInt(1) + val dmem_resp_waddr = io.dmem.resp.bits.tag.toUInt()(5,1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = io.dmem.resp.bits.replay && io.dmem.resp.bits.has_data