riscv/rocket-chip
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Chisel3 compatibility: use >>Int instead of >>UInt

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This commit is contained in:
Andrew Waterman
2015-08-05 15:28:31 -07:00
parent fb5524372d
commit 546205b174
6 changed files with 9 additions and 9 deletions
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2
rocket/src/main/scala/ptw.scala
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@ -125,7 +125,7 @@ class PTW(n: Int) extends CoreModule
val resp_err = state === s_error
val resp_val = state === s_done || resp_err
val r_resp_ppn = io.mem.req.bits.addr >> UInt(pgIdxBits)
val r_resp_ppn = io.mem.req.bits.addr >> pgIdxBits
val resp_ppn = Vec((0 until pgLevels-1).map(i => Cat(r_resp_ppn >> pgLevelBits*(pgLevels-i-1), r_req.addr(pgLevelBits*(pgLevels-i-1)-1,0))) :+ r_resp_ppn)(count)
for (i <- 0 until io.requestor.size) {