riscv/rocket-chip
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Chisel3 compatibility: use >>Int instead of >>UInt

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This commit is contained in:
Andrew Waterman
2015-08-05 15:28:31 -07:00
parent fb5524372d
commit 546205b174
6 changed files with 9 additions and 9 deletions
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4
rocket/src/main/scala/nbdcache.scala
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@ -332,7 +332,7 @@ class MSHRFile extends L1HellaCacheModule {
idxMatch(i) := mshr.io.idx_match
tagList(i) := mshr.io.tag
wbTagList(i) := mshr.io.wb_req.bits.addr_block >> UInt(idxBits)
wbTagList(i) := mshr.io.wb_req.bits.addr_block >> idxBits
alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy
mshr.io.req_pri_val := alloc_arb.io.in(i).ready
@ -437,7 +437,7 @@ class WritebackUnit extends L1HellaCacheModule {
// We reissue the meta read as it sets up the mux ctrl for s2_data_muxed
io.meta_read.valid := fire
io.meta_read.bits.idx := req_idx
io.meta_read.bits.tag := req.addr_block >> UInt(idxBits)
io.meta_read.bits.tag := req.addr_block >> idxBits
io.data_req.valid := fire
io.data_req.bits.way_en := req.way_en