riscv/rocket-chip
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Chisel3 compatibility: use >>Int instead of >>UInt

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This commit is contained in:
Andrew Waterman
2015-08-05 15:28:31 -07:00
parent fb5524372d
commit 546205b174
6 changed files with 9 additions and 9 deletions
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4
rocket/src/main/scala/icache.scala
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@@ -95,7 +95,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
io.ptw <> tlb.io.ptw
tlb.io.req.valid := !stall && !icmiss
tlb.io.req.bits.vpn := s1_pc >> UInt(pgIdxBits)
tlb.io.req.bits.vpn := s1_pc >> pgIdxBits
tlb.io.req.bits.asid := UInt(0)
tlb.io.req.bits.passthrough := Bool(false)
tlb.io.req.bits.instruction := Bool(true)
@@ -257,7 +257,7 @@ class ICache extends FrontendModule
// output signals
io.resp.valid := s2_hit
io.mem.acquire.valid := (state === s_request)
io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> blockOffBits)
// control state machine
switch (state) {