riscv/rocket-chip
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Chisel3 compatibility: use >>Int instead of >>UInt

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This commit is contained in:
Andrew Waterman
2015-08-05 15:28:31 -07:00
parent fb5524372d
commit 546205b174
6 changed files with 9 additions and 9 deletions
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2
rocket/src/main/scala/fpu.scala
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@ -215,7 +215,7 @@ class FPToInt extends Module
dcmp.io.a := in.in1
dcmp.io.b := in.in2
val dcmp_out = (~in.rm & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR
val dcmp_exc = (~in.rm & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UInt(4)
val dcmp_exc = (~in.rm & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << 4
val d2i = hardfloat.recodedFloatNToAny(in.in1, in.rm, in.typ ^ 1, 52, 12, 64)