riscv/rocket-chip
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add fp loads/stores

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This commit is contained in:
Andrew Waterman
2012-02-07 23:54:25 -08:00
parent 1be9d15944
commit 5403d069e9
7 changed files with 319 additions and 173 deletions
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46
rocket/src/main/scala/dpath.scala
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@ -34,6 +34,7 @@ class ioDpathAll extends Bundle()
val imem = new ioDpathImem();
val ptbr_wen = Bool(OUTPUT);
val ptbr = UFix(PADDR_BITS, OUTPUT);
val fpu = new ioDpathFPU();
}
class rocketDpath extends Component
@ -90,7 +91,6 @@ class rocketDpath extends Component
val ex_reg_ctrl_div_val = Reg(resetVal = Bool(false));
val ex_reg_ctrl_div_fn = Reg() { UFix() };
val ex_reg_ctrl_sel_wb = Reg() { UFix() };
val ex_reg_ctrl_wen = Reg(resetVal = Bool(false));
val ex_reg_ctrl_ren_pcr = Reg(resetVal = Bool(false));
val ex_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
val ex_wdata = Wire() { Bits() };
@ -104,7 +104,6 @@ class rocketDpath extends Component
val mem_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val mem_reg_ctrl_mul_val = Reg(resetVal = Bool(false));
val mem_reg_ctrl_div_val = Reg(resetVal = Bool(false));
val mem_reg_ctrl_wen = Reg(resetVal = Bool(false));
val mem_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
val mem_wdata = Wire() { Bits() };
@ -115,12 +114,11 @@ class rocketDpath extends Component
val wb_reg_wdata = Reg() { Bits() };
val wb_reg_raddr2 = Reg() { UFix() };
val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
val wb_wdata = Wire() { Bits() };
val r_dmem_resp_val = Reg(resetVal = Bool(false));
val r_dmem_resp_replay = Reg(resetVal = Bool(false));
val r_dmem_fp_replay = Reg(resetVal = Bool(false));
val r_dmem_resp_waddr = Reg() { UFix() };
// instruction fetch stage
@ -210,15 +208,15 @@ class rocketDpath extends Component
Mux(r_dmem_resp_replay, io.dmem.resp_data_subword,
Mux(io.ctrl.div_wb, div_result,
Mux(io.ctrl.mul_wb, mul_result,
Mux(id_raddr1 != UFix(0, 5) && (ex_reg_ctrl_wen || ex_reg_ctrl_ll_wb) && id_raddr1 === ex_reg_waddr, ex_wdata,
Mux(id_raddr1 != UFix(0, 5) && (mem_reg_ctrl_wen || mem_reg_ctrl_ll_wb) && id_raddr1 === mem_reg_waddr, mem_wdata,
Mux(id_raddr1 != UFix(0, 5) && (wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.ex_wen || ex_reg_ctrl_ll_wb) && id_raddr1 === ex_reg_waddr, ex_wdata,
Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.mem_wen || mem_reg_ctrl_ll_wb) && id_raddr1 === mem_reg_waddr, mem_wdata,
Mux(id_raddr1 != UFix(0, 5) && (io.ctrl.wb_wen || wb_reg_ctrl_ll_wb) && id_raddr1 === wb_reg_waddr, wb_wdata,
id_rdata1))))));
val id_rs2 =
Mux(id_raddr2 != UFix(0, 5) && (ex_reg_ctrl_wen || ex_reg_ctrl_ll_wb) && id_raddr2 === ex_reg_waddr, ex_wdata,
Mux(id_raddr2 != UFix(0, 5) && (mem_reg_ctrl_wen || mem_reg_ctrl_ll_wb) && id_raddr2 === mem_reg_waddr, mem_wdata,
Mux(id_raddr2 != UFix(0, 5) && (wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.ex_wen || ex_reg_ctrl_ll_wb) && id_raddr2 === ex_reg_waddr, ex_wdata,
Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.mem_wen || mem_reg_ctrl_ll_wb) && id_raddr2 === mem_reg_waddr, mem_wdata,
Mux(id_raddr2 != UFix(0, 5) && (io.ctrl.wb_wen || wb_reg_ctrl_ll_wb) && id_raddr2 === wb_reg_waddr, wb_wdata,
id_rdata2)));
io.ctrl.inst := id_reg_inst;
@ -244,7 +242,6 @@ class rocketDpath extends Component
ex_reg_valid <== Bool(false);
ex_reg_ctrl_div_val <== Bool(false);
ex_reg_ctrl_mul_val <== Bool(false);
ex_reg_ctrl_wen <== Bool(false);
ex_reg_ctrl_wen_pcr <== Bool(false);
ex_reg_ctrl_eret <== Bool(false);
}
@ -252,7 +249,6 @@ class rocketDpath extends Component
ex_reg_valid <== id_reg_valid;
ex_reg_ctrl_div_val <== io.ctrl.div_val;
ex_reg_ctrl_mul_val <== io.ctrl.mul_val;
ex_reg_ctrl_wen <== io.ctrl.wen;
ex_reg_ctrl_wen_pcr <== io.ctrl.wen_pcr;
ex_reg_ctrl_eret <== io.ctrl.id_eret;
}
@ -307,8 +303,14 @@ class rocketDpath extends Component
// D$ request interface (registered inside D$ module)
// other signals (req_val, req_rdy) connect to control module
io.dmem.req_addr := ex_jr_target_extended.toUFix;
io.dmem.req_data := ex_reg_rs2;
io.dmem.req_tag := ex_reg_waddr;
if (HAVE_FPU) {
io.dmem.req_data := Mux(io.ctrl.ex_fp_val, io.fpu.store_data, ex_reg_rs2)
io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val).toUFix
}
else {
io.dmem.req_data := ex_reg_rs2
io.dmem.req_tag := Cat(ex_reg_waddr, Bool(false)).toUFix
}
// processor control regfile read
pcr.io.r.en := ex_reg_ctrl_ren_pcr | ex_reg_ctrl_eret;
@ -361,12 +363,10 @@ class rocketDpath extends Component
when (io.ctrl.killx) {
mem_reg_valid <== Bool(false);
mem_reg_ctrl_wen <== Bool(false);
mem_reg_ctrl_wen_pcr <== Bool(false);
}
otherwise {
mem_reg_valid <== ex_reg_valid;
mem_reg_ctrl_wen <== ex_reg_ctrl_wen;
mem_reg_ctrl_wen_pcr <== ex_reg_ctrl_wen_pcr;
}
@ -379,9 +379,10 @@ class rocketDpath extends Component
// 32/64 bit load handling (moved to earlier in file)
// writeback stage
r_dmem_resp_val <== io.dmem.resp_val;
r_dmem_resp_replay <== io.dmem.resp_replay;
r_dmem_resp_waddr <== io.dmem.resp_tag.toUFix
val dmem_resp_fpu = if (HAVE_FPU) io.dmem.resp_tag(0).toBool else Bool(false)
r_dmem_resp_replay <== io.dmem.resp_replay && !dmem_resp_fpu;
r_dmem_fp_replay <== io.dmem.resp_replay && dmem_resp_fpu;
r_dmem_resp_waddr <== io.dmem.resp_tag.toUFix >> UFix(1)
wb_reg_pc <== mem_reg_pc;
wb_reg_waddr <== mem_reg_waddr;
@ -391,26 +392,27 @@ class rocketDpath extends Component
when (io.ctrl.killm) {
wb_reg_valid <== Bool(false);
wb_reg_ctrl_wen <== Bool(false);
wb_reg_ctrl_wen_pcr <== Bool(false);
}
otherwise {
wb_reg_valid <== mem_reg_valid;
wb_reg_ctrl_wen <== mem_reg_ctrl_wen && !io.dmem.resp_miss;
wb_reg_ctrl_wen_pcr <== mem_reg_ctrl_wen_pcr;
}
// regfile write
wb_wdata := Mux(Reg(io.ctrl.mem_load), io.dmem.resp_data_subword, wb_reg_wdata)
rfile.io.w0.addr := wb_reg_waddr;
rfile.io.w0.en := wb_reg_ctrl_wen || wb_reg_ctrl_ll_wb;
rfile.io.w0.en := io.ctrl.wb_wen || wb_reg_ctrl_ll_wb;
rfile.io.w0.data := wb_wdata
io.ctrl.wb_waddr := wb_reg_waddr;
io.ctrl.mem_wb := r_dmem_resp_replay;
// scoreboard clear (for div/mul and D$ load miss writebacks)
io.ctrl.sboard_clr := id_ctrl_ll_wb;
io.ctrl.sboard_clra := id_waddr;
io.ctrl.fp_sboard_clr := r_dmem_fp_replay;
io.ctrl.fp_sboard_clra := r_dmem_resp_waddr;
// processor control regfile write
pcr.io.w.addr := wb_reg_raddr2;