riscv/rocket-chip
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another fix for AXI -> AHB converter

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This commit is contained in:
Howard Mao 2016-06-01 11:35:17 -07:00
parent d0988902f2
commit 53a0e6cb9c
1 changed files with 1 additions and 1 deletions
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2
junctions/src/main/scala/hasti.scala
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@ -384,7 +384,7 @@ class HastiMasterIONastiIOConverter(implicit p: Parameters) extends HastiModule(
val is_rtrans = (state === s_read) && val is_rtrans = (state === s_read) &&
(io.hasti.htrans === HTRANS_SEQ || (io.hasti.htrans === HTRANS_SEQ ||
io.hasti.htrans === HTRANS_NONSEQ) io.hasti.htrans === HTRANS_NONSEQ)
val rvalid = Reg(next = is_rtrans) val rvalid = Reg(is_rtrans, io.hasti.hready)
io.nasti.aw.ready := (state === s_idle) io.nasti.aw.ready := (state === s_idle)
io.nasti.ar.ready := (state === s_idle) && !io.nasti.aw.valid io.nasti.ar.ready := (state === s_idle) && !io.nasti.aw.valid