Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles
This commit is contained in:
Henry Cook
parent
17d2bd8926
commit
538b23c223
@ -13,10 +13,10 @@ OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
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DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
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generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
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cd $(basedir)/sbt && $(SBT) "project referencechip" "run elaborate $(MODEL) c ../emulator/generated-src"
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cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src"
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generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
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cd $(basedir)/sbt && $(SBT) "project referencechip" "run elaborate $(MODEL) c ../emulator/generated-src-debug --debug --vcd"
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cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src-debug --debug --vcd"
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$(MODEL).o: %.o: generated-src/%.cpp
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$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
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@ -46,7 +46,7 @@ clean:
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rm -rf *.o emulator emulator-debug generated-src generated-src-debug DVEfiles output
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test:
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cd $(basedir)/sbt && $(SBT) "project referencechip" "~run test $(MODEL) c ../emulator/generated-src"
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cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast"
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#--------------------------------------------------------------------
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# Run assembly tests and benchmarks
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@ -1,48 +1,74 @@
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import sbt._
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import Keys._
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//val extracted: Extracted = Project.extract(state)
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//import extracted._
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object BuildSettings extends Build {
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val buildOrganization = "berkeley"
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val buildVersion = "1.1"
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val buildScalaVersion = "2.9.2"
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val packageDependencies = TaskKey[Seq[java.io.File]]("package-dependencies", "get package deps")
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val elaborateTask = TaskKey[Unit]("elaborate", "convert chisel components into backend source code")
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val chiselDebug = SettingKey[Boolean]("chisel-debug", "generated backend sources with debug signals")
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val chiselArgsDebug = SettingKey[Seq[String]]("chisel-args-debug", "additional chisel args for debug backend signals")
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val chiselArgsC = SettingKey[Seq[String]]("chisel-args-c", "default chisel args for c backend")
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val chiselArgsVlsi = SettingKey[Seq[String]]("chisel-args-vlsi", "default chisel args for vlsi backend")
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val chiselArgsFpga = SettingKey[Seq[String]]("chisel-args-fpga", "default chisel args for fpga backend")
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val buildSettings = Defaults.defaultSettings ++ Seq (
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//unmanagedBase <<= baseDirectory { base => base / ".." / custom_lib" },
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organization := buildOrganization,
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version := buildVersion,
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scalaVersion := buildScalaVersion,
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elaborateTask <<= fullClasspath in Runtime map {
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(cp: Classpath) => {
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val projName = "ReferenceChip"
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val dir = "../emulator/generated-src"
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val backend = "c"
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val chiselArgs = Array[String]( "--targetDir", dir, "--backend", backend)
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val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader)
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val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$")
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val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null)
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val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]])
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val component = classLoader.loadClass(projName+".Top")
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val generator = () => component.newInstance()
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chiselMain.invoke(chiselMainObject, Array(chiselArgs, generator):_*)
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}
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}
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chiselDebug := false,
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chiselArgsDebug := Seq("--debug","--vcd"),
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chiselArgsC := "--targetDir ../emulator/generated-src --backend c".split(" "),
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chiselArgsFpga := "--targetDir ../fpga/generated-src --backend fpga".split(" "),
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chiselArgsVlsi := "--targetDir ../vlsi/generated-src --backend v".split(" ")
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)
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lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings)
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lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
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lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(hardfloat,chisel)
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lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel)
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lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore,hwacha,hardfloat,chisel)
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lazy val referencechip = Project("referencechip", file("referencechip"), settings = buildSettings) dependsOn(chisel,rocket)
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lazy val referencechip = Project("referencechip", file("referencechip"), settings = buildSettings ++ chipSettings) dependsOn(chisel,rocket)
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val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
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val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")
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val chipSettings = Seq(
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elaborateTask <<= inputTask { (argTask: TaskKey[Seq[String]]) =>
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(argTask, fullClasspath in Runtime, thisProject, chiselDebug, chiselArgsDebug) map {
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(args: Seq[String], cp: Classpath, pr: ResolvedProject, debug: Boolean, debugArgs: Seq[String]) => {
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val numArgs = 1
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require(args.length >= numArgs, "syntax: elaborate <component> [chisel args]")
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val projectName = pr.id
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val packageName = projectName //TODO: valid convention?
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val componentName = args(0)
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val optionalArgs = if(debug) debugArgs else Nil
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val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader)
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val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$")
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val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null)
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val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]])
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val chiselArgs = args.drop(numArgs) ++ optionalArgs
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val component = classLoader.loadClass(packageName+"."+componentName)
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val generator = () => component.newInstance()
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chiselMain.invoke(chiselMainObject, Array(chiselArgs.toArray, generator):_*)
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}
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}
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},
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makeTask <<= inputTask { (argTask: TaskKey[Seq[String]]) =>
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(argTask) map {
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(args: Seq[String]) => {
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require(args.length >= 2, "syntax: <dir> <target>")
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val makeDir = args(0)
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val target = args(1)
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val jobs = java.lang.Runtime.getRuntime.availableProcessors
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val make = "make -C" + makeDir + " -j" + jobs + " " + target
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make!
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}
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}
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}
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)
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}
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@ -1,51 +0,0 @@
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package ReferenceChip
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import sys.process._
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import Chisel._
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object Main
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{
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def classOf(x: String) = try {
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Class.forName(x)
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} catch {
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case _: ClassNotFoundException => {
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val myPackage = getClass.getName.reverse.dropWhile(_ != '.').reverse
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Class.forName(myPackage+x)
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}
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}
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def main(allArgs: Array[String]): Unit = {
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require(allArgs.length >= 4, "syntax: run <command> <component> <backend> <dir> [args]")
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val cmd = allArgs(0)
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val compName = allArgs(1)
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val backendName = allArgs(2)
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val dir = allArgs(3)
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val backend = try {
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classOf(backendName).getName
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} catch {
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case _ => backendName
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}
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println("I'm gonna "+cmd+" component "+compName+" with backend "+backendName+"...")
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val comp = classOf(compName)
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val chiselArgs = allArgs.drop(4) ++ Array("--targetDir", dir, "--backend", backend)
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val makeDir = dir+"/.."
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val jobs = Runtime.getRuntime.availableProcessors
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val make = "make -C" + makeDir + " -j" + jobs
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val action = cmd match {
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case "elaborate" => () =>
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case "build" => () => make!
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case "test" => () => {
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if ((make+" run-fast"!) == 0) println("PASSED")
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else println("FAILED")
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}
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case _ => throw new IllegalArgumentException("unknown command "+cmd)
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}
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chiselMain(chiselArgs, () => comp.newInstance.asInstanceOf[Component])
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action()
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}
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}
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@ -1,4 +1,4 @@
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package ReferenceChip
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package referencechip
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import Chisel._
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import Node._
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