From 538b23c223478dd2b13ab720d328397a416c9510 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 23 Oct 2012 12:51:37 -0700 Subject: [PATCH] Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles --- emulator/Makefile | 6 +-- project/build.scala | 72 ++++++++++++++++++++++----------- src/main/scala/Main.scala | 51 ----------------------- src/main/scala/RocketChip.scala | 2 +- 4 files changed, 53 insertions(+), 78 deletions(-) delete mode 100644 src/main/scala/Main.scala diff --git a/emulator/Makefile b/emulator/Makefile index a0a65a0e..b8e8caaa 100644 --- a/emulator/Makefile +++ b/emulator/Makefile @@ -13,10 +13,10 @@ OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL)) DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL)) generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala - cd $(basedir)/sbt && $(SBT) "project referencechip" "run elaborate $(MODEL) c ../emulator/generated-src" + cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src" generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala - cd $(basedir)/sbt && $(SBT) "project referencechip" "run elaborate $(MODEL) c ../emulator/generated-src-debug --debug --vcd" + cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src-debug --debug --vcd" $(MODEL).o: %.o: generated-src/%.cpp $(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $< @@ -46,7 +46,7 @@ clean: rm -rf *.o emulator emulator-debug generated-src generated-src-debug DVEfiles output test: - cd $(basedir)/sbt && $(SBT) "project referencechip" "~run test $(MODEL) c ../emulator/generated-src" + cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast" #-------------------------------------------------------------------- # Run assembly tests and benchmarks diff --git a/project/build.scala b/project/build.scala index 4e6999a0..27b49ed5 100644 --- a/project/build.scala +++ b/project/build.scala @@ -1,48 +1,74 @@ import sbt._ import Keys._ +//val extracted: Extracted = Project.extract(state) +//import extracted._ object BuildSettings extends Build { val buildOrganization = "berkeley" val buildVersion = "1.1" val buildScalaVersion = "2.9.2" - val packageDependencies = TaskKey[Seq[java.io.File]]("package-dependencies", "get package deps") - val elaborateTask = TaskKey[Unit]("elaborate", "convert chisel components into backend source code") - + val chiselDebug = SettingKey[Boolean]("chisel-debug", "generated backend sources with debug signals") + val chiselArgsDebug = SettingKey[Seq[String]]("chisel-args-debug", "additional chisel args for debug backend signals") + val chiselArgsC = SettingKey[Seq[String]]("chisel-args-c", "default chisel args for c backend") + val chiselArgsVlsi = SettingKey[Seq[String]]("chisel-args-vlsi", "default chisel args for vlsi backend") + val chiselArgsFpga = SettingKey[Seq[String]]("chisel-args-fpga", "default chisel args for fpga backend") val buildSettings = Defaults.defaultSettings ++ Seq ( //unmanagedBase <<= baseDirectory { base => base / ".." / custom_lib" }, organization := buildOrganization, version := buildVersion, scalaVersion := buildScalaVersion, - elaborateTask <<= fullClasspath in Runtime map { - (cp: Classpath) => { - val projName = "ReferenceChip" - val dir = "../emulator/generated-src" - val backend = "c" - val chiselArgs = Array[String]( "--targetDir", dir, "--backend", backend) - val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader) - val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$") - val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null) - val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]]) - val component = classLoader.loadClass(projName+".Top") - val generator = () => component.newInstance() - chiselMain.invoke(chiselMainObject, Array(chiselArgs, generator):_*) - } - } - + chiselDebug := false, + chiselArgsDebug := Seq("--debug","--vcd"), + chiselArgsC := "--targetDir ../emulator/generated-src --backend c".split(" "), + chiselArgsFpga := "--targetDir ../fpga/generated-src --backend fpga".split(" "), + chiselArgsVlsi := "--targetDir ../vlsi/generated-src --backend v".split(" ") ) - lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings) lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel) lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(hardfloat,chisel) lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore,hwacha,hardfloat,chisel) - lazy val referencechip = Project("referencechip", file("referencechip"), settings = buildSettings) dependsOn(chisel,rocket) + lazy val referencechip = Project("referencechip", file("referencechip"), settings = buildSettings ++ chipSettings) dependsOn(chisel,rocket) + val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") + val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command") - - + val chipSettings = Seq( + elaborateTask <<= inputTask { (argTask: TaskKey[Seq[String]]) => + (argTask, fullClasspath in Runtime, thisProject, chiselDebug, chiselArgsDebug) map { + (args: Seq[String], cp: Classpath, pr: ResolvedProject, debug: Boolean, debugArgs: Seq[String]) => { + val numArgs = 1 + require(args.length >= numArgs, "syntax: elaborate [chisel args]") + val projectName = pr.id + val packageName = projectName //TODO: valid convention? + val componentName = args(0) + val optionalArgs = if(debug) debugArgs else Nil + val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader) + val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$") + val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null) + val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]]) + val chiselArgs = args.drop(numArgs) ++ optionalArgs + val component = classLoader.loadClass(packageName+"."+componentName) + val generator = () => component.newInstance() + chiselMain.invoke(chiselMainObject, Array(chiselArgs.toArray, generator):_*) + } + } + }, + makeTask <<= inputTask { (argTask: TaskKey[Seq[String]]) => + (argTask) map { + (args: Seq[String]) => { + require(args.length >= 2, "syntax: ") + val makeDir = args(0) + val target = args(1) + val jobs = java.lang.Runtime.getRuntime.availableProcessors + val make = "make -C" + makeDir + " -j" + jobs + " " + target + make! + } + } + } + ) } diff --git a/src/main/scala/Main.scala b/src/main/scala/Main.scala deleted file mode 100644 index 3c626167..00000000 --- a/src/main/scala/Main.scala +++ /dev/null @@ -1,51 +0,0 @@ -package ReferenceChip - -import sys.process._ -import Chisel._ - -object Main -{ - def classOf(x: String) = try { - Class.forName(x) - } catch { - case _: ClassNotFoundException => { - val myPackage = getClass.getName.reverse.dropWhile(_ != '.').reverse - Class.forName(myPackage+x) - } - } - - def main(allArgs: Array[String]): Unit = { - require(allArgs.length >= 4, "syntax: run [args]") - val cmd = allArgs(0) - val compName = allArgs(1) - val backendName = allArgs(2) - val dir = allArgs(3) - - val backend = try { - classOf(backendName).getName - } catch { - case _ => backendName - } - - println("I'm gonna "+cmd+" component "+compName+" with backend "+backendName+"...") - val comp = classOf(compName) - - val chiselArgs = allArgs.drop(4) ++ Array("--targetDir", dir, "--backend", backend) - - val makeDir = dir+"/.." - val jobs = Runtime.getRuntime.availableProcessors - val make = "make -C" + makeDir + " -j" + jobs - val action = cmd match { - case "elaborate" => () => - case "build" => () => make! - case "test" => () => { - if ((make+" run-fast"!) == 0) println("PASSED") - else println("FAILED") - } - case _ => throw new IllegalArgumentException("unknown command "+cmd) - } - - chiselMain(chiselArgs, () => comp.newInstance.asInstanceOf[Component]) - action() - } -} diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 41f6fc26..14eb9fa8 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -1,4 +1,4 @@ -package ReferenceChip +package referencechip import Chisel._ import Node._