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Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles

This commit is contained in:
Henry Cook 2012-10-23 12:51:37 -07:00
parent 17d2bd8926
commit 538b23c223
4 changed files with 53 additions and 78 deletions

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@ -13,10 +13,10 @@ OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL)) DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "run elaborate $(MODEL) c ../emulator/generated-src" cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src"
generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "run elaborate $(MODEL) c ../emulator/generated-src-debug --debug --vcd" cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src-debug --debug --vcd"
$(MODEL).o: %.o: generated-src/%.cpp $(MODEL).o: %.o: generated-src/%.cpp
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $< $(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
@ -46,7 +46,7 @@ clean:
rm -rf *.o emulator emulator-debug generated-src generated-src-debug DVEfiles output rm -rf *.o emulator emulator-debug generated-src generated-src-debug DVEfiles output
test: test:
cd $(basedir)/sbt && $(SBT) "project referencechip" "~run test $(MODEL) c ../emulator/generated-src" cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast"
#-------------------------------------------------------------------- #--------------------------------------------------------------------
# Run assembly tests and benchmarks # Run assembly tests and benchmarks

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@ -1,48 +1,74 @@
import sbt._ import sbt._
import Keys._ import Keys._
//val extracted: Extracted = Project.extract(state)
//import extracted._
object BuildSettings extends Build { object BuildSettings extends Build {
val buildOrganization = "berkeley" val buildOrganization = "berkeley"
val buildVersion = "1.1" val buildVersion = "1.1"
val buildScalaVersion = "2.9.2" val buildScalaVersion = "2.9.2"
val packageDependencies = TaskKey[Seq[java.io.File]]("package-dependencies", "get package deps") val chiselDebug = SettingKey[Boolean]("chisel-debug", "generated backend sources with debug signals")
val elaborateTask = TaskKey[Unit]("elaborate", "convert chisel components into backend source code") val chiselArgsDebug = SettingKey[Seq[String]]("chisel-args-debug", "additional chisel args for debug backend signals")
val chiselArgsC = SettingKey[Seq[String]]("chisel-args-c", "default chisel args for c backend")
val chiselArgsVlsi = SettingKey[Seq[String]]("chisel-args-vlsi", "default chisel args for vlsi backend")
val chiselArgsFpga = SettingKey[Seq[String]]("chisel-args-fpga", "default chisel args for fpga backend")
val buildSettings = Defaults.defaultSettings ++ Seq ( val buildSettings = Defaults.defaultSettings ++ Seq (
//unmanagedBase <<= baseDirectory { base => base / ".." / custom_lib" }, //unmanagedBase <<= baseDirectory { base => base / ".." / custom_lib" },
organization := buildOrganization, organization := buildOrganization,
version := buildVersion, version := buildVersion,
scalaVersion := buildScalaVersion, scalaVersion := buildScalaVersion,
elaborateTask <<= fullClasspath in Runtime map { chiselDebug := false,
(cp: Classpath) => { chiselArgsDebug := Seq("--debug","--vcd"),
val projName = "ReferenceChip" chiselArgsC := "--targetDir ../emulator/generated-src --backend c".split(" "),
val dir = "../emulator/generated-src" chiselArgsFpga := "--targetDir ../fpga/generated-src --backend fpga".split(" "),
val backend = "c" chiselArgsVlsi := "--targetDir ../vlsi/generated-src --backend v".split(" ")
val chiselArgs = Array[String]( "--targetDir", dir, "--backend", backend)
val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader)
val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$")
val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null)
val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]])
val component = classLoader.loadClass(projName+".Top")
val generator = () => component.newInstance()
chiselMain.invoke(chiselMainObject, Array(chiselArgs, generator):_*)
}
}
) )
lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings) lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings)
lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel) lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(hardfloat,chisel) lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(hardfloat,chisel)
lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel) lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel)
lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore,hwacha,hardfloat,chisel) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore,hwacha,hardfloat,chisel)
lazy val referencechip = Project("referencechip", file("referencechip"), settings = buildSettings) dependsOn(chisel,rocket) lazy val referencechip = Project("referencechip", file("referencechip"), settings = buildSettings ++ chipSettings) dependsOn(chisel,rocket)
val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")
val chipSettings = Seq(
elaborateTask <<= inputTask { (argTask: TaskKey[Seq[String]]) =>
(argTask, fullClasspath in Runtime, thisProject, chiselDebug, chiselArgsDebug) map {
(args: Seq[String], cp: Classpath, pr: ResolvedProject, debug: Boolean, debugArgs: Seq[String]) => {
val numArgs = 1
require(args.length >= numArgs, "syntax: elaborate <component> [chisel args]")
val projectName = pr.id
val packageName = projectName //TODO: valid convention?
val componentName = args(0)
val optionalArgs = if(debug) debugArgs else Nil
val classLoader = new java.net.URLClassLoader(cp.map(_.data.toURL).toArray, cp.getClass.getClassLoader)
val chiselMainClass = classLoader.loadClass("Chisel.chiselMain$")
val chiselMainObject = chiselMainClass.getDeclaredFields.head.get(null)
val chiselMain = chiselMainClass.getMethod("run", classOf[Array[String]], classOf[Function0[_]])
val chiselArgs = args.drop(numArgs) ++ optionalArgs
val component = classLoader.loadClass(packageName+"."+componentName)
val generator = () => component.newInstance()
chiselMain.invoke(chiselMainObject, Array(chiselArgs.toArray, generator):_*)
}
}
},
makeTask <<= inputTask { (argTask: TaskKey[Seq[String]]) =>
(argTask) map {
(args: Seq[String]) => {
require(args.length >= 2, "syntax: <dir> <target>")
val makeDir = args(0)
val target = args(1)
val jobs = java.lang.Runtime.getRuntime.availableProcessors
val make = "make -C" + makeDir + " -j" + jobs + " " + target
make!
}
}
}
)
} }

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@ -1,51 +0,0 @@
package ReferenceChip
import sys.process._
import Chisel._
object Main
{
def classOf(x: String) = try {
Class.forName(x)
} catch {
case _: ClassNotFoundException => {
val myPackage = getClass.getName.reverse.dropWhile(_ != '.').reverse
Class.forName(myPackage+x)
}
}
def main(allArgs: Array[String]): Unit = {
require(allArgs.length >= 4, "syntax: run <command> <component> <backend> <dir> [args]")
val cmd = allArgs(0)
val compName = allArgs(1)
val backendName = allArgs(2)
val dir = allArgs(3)
val backend = try {
classOf(backendName).getName
} catch {
case _ => backendName
}
println("I'm gonna "+cmd+" component "+compName+" with backend "+backendName+"...")
val comp = classOf(compName)
val chiselArgs = allArgs.drop(4) ++ Array("--targetDir", dir, "--backend", backend)
val makeDir = dir+"/.."
val jobs = Runtime.getRuntime.availableProcessors
val make = "make -C" + makeDir + " -j" + jobs
val action = cmd match {
case "elaborate" => () =>
case "build" => () => make!
case "test" => () => {
if ((make+" run-fast"!) == 0) println("PASSED")
else println("FAILED")
}
case _ => throw new IllegalArgumentException("unknown command "+cmd)
}
chiselMain(chiselArgs, () => comp.newInstance.asInstanceOf[Component])
action()
}
}

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@ -1,4 +1,4 @@
package ReferenceChip package referencechip
import Chisel._ import Chisel._
import Node._ import Node._