riscv/rocket-chip
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Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles

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This commit is contained in:
Henry Cook
2012-10-23 12:51:37 -07:00
parent 17d2bd8926
commit 538b23c223
4 changed files with 53 additions and 78 deletions
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6
emulator/Makefile
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@ -13,10 +13,10 @@ OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
generated-src/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "run elaborate $(MODEL) c ../emulator/generated-src"
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src"
generated-src-debug/$(MODEL).cpp: $(basedir)/riscv-rocket/src/*.scala $(basedir)/riscv-hwacha/src/*.scala $(basedir)/chisel/src/main/scala/* $(basedir)/uncore/src/*.scala
cd $(basedir)/sbt && $(SBT) "project referencechip" "run elaborate $(MODEL) c ../emulator/generated-src-debug --debug --vcd"
cd $(basedir)/sbt && $(SBT) "project referencechip" "elaborate $(MODEL) --backend c --targetDir ../emulator/generated-src-debug --debug --vcd"
$(MODEL).o: %.o: generated-src/%.cpp
$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
@ -46,7 +46,7 @@ clean:
rm -rf *.o emulator emulator-debug generated-src generated-src-debug DVEfiles output
test:
cd $(basedir)/sbt && $(SBT) "project referencechip" "~run test $(MODEL) c ../emulator/generated-src"
cd $(basedir)/sbt && $(SBT) "project referencechip" "~make ../emulator run-fast"
#--------------------------------------------------------------------
# Run assembly tests and benchmarks