riscv/rocket-chip
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coreplex: move buffers inside the coreplex

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This should make hierarchical place and route easier.
This commit is contained in:
Wesley W. Terpstra
2017-03-24 22:53:46 -07:00
parent 5bbb75e078
commit 537274b645
2 changed files with 10 additions and 6 deletions
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src/main/scala/rocketchip/BaseTop.scala
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@ -36,8 +36,8 @@ trait HasTopLevelNetworks extends HasPeripheryParameters {
val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
val intBus = LazyModule(new IntXbar) // Interrupts
val fsb = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2
val bsb = LazyModule(new TLBuffer) // Slave devices talking to the backside of the L2
val fsb = LazyModule(new TLBuffer(BufferParams.none)) // Master devices talking to the frontside of the L2
val bsb = LazyModule(new TLBuffer(BufferParams.none)) // Slave devices talking to the backside of the L2
val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
// The peripheryBus hangs off of socBus;