diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala
index db049848..3ee9a279 100644
--- a/src/main/scala/coreplex/CoreplexNetwork.scala
+++ b/src/main/scala/coreplex/CoreplexNetwork.scala
@@ -31,7 +31,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
   intBar.intnode := mmioInt
 
   // Allows a variable number of inputs from outside to the Xbar
-  l1tol2.node :=* l2in
+  private val l2in_buffer = LazyModule(new TLBuffer)
+  l1tol2.node :=* l2in_buffer.node
+  l2in_buffer.node :=* l2in
+
+  private val l2out_buffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none))
+  l2out :*= l2out_buffer.node
+  l2out_buffer.node :*= l1tol2.node
 
   cbus.node :=
     TLBuffer()(
@@ -43,8 +49,6 @@ trait CoreplexNetwork extends HasCoreplexParameters {
     TLWidthWidget(l1tol2_beatBytes)(
     l1tol2.node)
 
-  l2out :*= l1tol2.node
-
   val root = new Device {
     def describe(resources: ResourceBindings): Description = {
       val width = resources("width").map(_.value)
@@ -134,7 +138,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
     val node = TLOutputNode()
     for (bank <- 0 until l2Config.nBanksPerChannel) {
       val offset = (bank * l2Config.nMemoryChannels) + channel
-      in := TLBuffer(BufferParams.flow)(l1tol2.node)
+      in := TLBuffer(BufferParams.flow, BufferParams.none)(l1tol2.node)
       node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out)
     }
     node
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index d671b8e7..d74c8499 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -36,8 +36,8 @@ trait HasTopLevelNetworks extends HasPeripheryParameters {
   val socBus = LazyModule(new TLXbar)          // Wide or unordered-access slave devices (TL-UH)
   val peripheryBus = LazyModule(new TLXbar)    // Narrow and ordered-access slave devices (TL-UL)
   val intBus = LazyModule(new IntXbar)         // Interrupts
-  val fsb = LazyModule(new TLBuffer)           // Master devices talking to the frontside of the L2
-  val bsb = LazyModule(new TLBuffer)           // Slave devices talking to the backside of the L2
+  val fsb = LazyModule(new TLBuffer(BufferParams.none))          // Master devices talking to the frontside of the L2
+  val bsb = LazyModule(new TLBuffer(BufferParams.none))          // Slave devices talking to the backside of the L2
   val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
 
   // The peripheryBus hangs off of socBus;