riscv/rocket-chip
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coreplex: move buffers inside the coreplex

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This should make hierarchical place and route easier.
This commit is contained in:
Wesley W. Terpstra
2017-03-24 22:53:46 -07:00
parent 5bbb75e078
commit 537274b645
2 changed files with 10 additions and 6 deletions
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12
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -31,7 +31,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
intBar.intnode := mmioInt
// Allows a variable number of inputs from outside to the Xbar
l1tol2.node :=* l2in
private val l2in_buffer = LazyModule(new TLBuffer)
l1tol2.node :=* l2in_buffer.node
l2in_buffer.node :=* l2in
private val l2out_buffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none))
l2out :*= l2out_buffer.node
l2out_buffer.node :*= l1tol2.node
cbus.node :=
TLBuffer()(
@ -43,8 +49,6 @@ trait CoreplexNetwork extends HasCoreplexParameters {
TLWidthWidget(l1tol2_beatBytes)(
l1tol2.node)
l2out :*= l1tol2.node
val root = new Device {
def describe(resources: ResourceBindings): Description = {
val width = resources("width").map(_.value)
@ -134,7 +138,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
val node = TLOutputNode()
for (bank <- 0 until l2Config.nBanksPerChannel) {
val offset = (bank * l2Config.nMemoryChannels) + channel
in := TLBuffer(BufferParams.flow)(l1tol2.node)
in := TLBuffer(BufferParams.flow, BufferParams.none)(l1tol2.node)
node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out)
}
node