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Chisel3: bulk connect is not commutative

We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
This commit is contained in:
Andrew Waterman 2015-08-01 21:11:25 -07:00
parent 6c0e1e33ab
commit 52fc34a138
4 changed files with 34 additions and 32 deletions

View File

@ -93,7 +93,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
btb.io.ras_update := io.cpu.ras_update
btb.io.invalidate := io.cpu.invalidate || io.ptw.invalidate
tlb.io.ptw <> io.ptw
io.ptw <> tlb.io.ptw
tlb.io.req.valid := !stall && !icmiss
tlb.io.req.bits.vpn := s1_pc >> UInt(pgIdxBits)
tlb.io.req.bits.asid := UInt(0)
@ -101,7 +101,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
tlb.io.req.bits.instruction := Bool(true)
tlb.io.req.bits.store := Bool(false)
icache.io.mem <> io.mem
io.mem <> icache.io.mem
icache.io.req.valid := !stall && !s0_same_block
icache.io.req.bits.idx := io.cpu.npc
icache.io.invalidate := io.cpu.invalidate

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@ -341,11 +341,11 @@ class MSHRFile extends L1HellaCacheModule {
mshr.io.req_bits := io.req.bits
mshr.io.req_bits.sdq_id := sdq_alloc_id
mshr.io.meta_read <> meta_read_arb.io.in(i)
mshr.io.meta_write <> meta_write_arb.io.in(i)
mshr.io.mem_req <> mem_req_arb.io.in(i)
mshr.io.wb_req <> wb_req_arb.io.in(i)
mshr.io.replay <> replay_arb.io.in(i)
meta_read_arb.io.in(i) <> mshr.io.meta_read
meta_write_arb.io.in(i) <> mshr.io.meta_write
mem_req_arb.io.in(i) <> mshr.io.mem_req
wb_req_arb.io.in(i) <> mshr.io.wb_req
replay_arb.io.in(i) <> mshr.io.replay
mshr.io.mem_grant.valid := io.mem_grant.valid &&
io.mem_grant.bits.client_xact_id === UInt(i)
@ -362,10 +362,10 @@ class MSHRFile extends L1HellaCacheModule {
alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match
meta_read_arb.io.out <> io.meta_read
meta_write_arb.io.out <> io.meta_write
mem_req_arb.io.out <> io.mem_req
wb_req_arb.io.out <> io.wb_req
io.meta_read <> meta_read_arb.io.out
io.meta_write <> meta_write_arb.io.out
io.mem_req <> mem_req_arb.io.out
io.wb_req <> wb_req_arb.io.out
io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
io.secondary_miss := idx_match
@ -624,7 +624,7 @@ class HellaCache extends L1HellaCacheModule {
val s1_readwrite = s1_read || s1_write || isPrefetch(s1_req.cmd)
val dtlb = Module(new TLB)
dtlb.io.ptw <> io.ptw
io.ptw <> dtlb.io.ptw
dtlb.io.req.valid := s1_valid_masked && s1_readwrite && !s1_req.phys
dtlb.io.req.bits.passthrough := s1_req.phys
dtlb.io.req.bits.asid := UInt(0)
@ -684,8 +684,8 @@ class HellaCache extends L1HellaCacheModule {
val meta = Module(new MetadataArray(onReset _))
val metaReadArb = Module(new Arbiter(new MetaReadReq, 5))
val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2))
metaReadArb.io.out <> meta.io.read
metaWriteArb.io.out <> meta.io.write
meta.io.read <> metaReadArb.io.out
meta.io.write <> metaWriteArb.io.out
// data
val data = Module(new DataArray)
@ -808,16 +808,16 @@ class HellaCache extends L1HellaCacheModule {
// probes and releases
val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData()))
releaseArb.io.out <> io.mem.release
io.mem.release <> releaseArb.io.out
prober.io.req.valid := io.mem.probe.valid && !lrsc_valid
io.mem.probe.ready := prober.io.req.ready && !lrsc_valid
prober.io.req.bits := io.mem.probe.bits
prober.io.rep <> releaseArb.io.in(1)
releaseArb.io.in(1) <> prober.io.rep
prober.io.way_en := s2_tag_match_way
prober.io.block_state := s2_hit_state
prober.io.meta_read <> metaReadArb.io.in(2)
prober.io.meta_write <> metaWriteArb.io.in(1)
metaReadArb.io.in(2) <> prober.io.meta_read
metaWriteArb.io.in(1) <> prober.io.meta_write
prober.io.mshr_rdy := mshrs.io.probe_rdy
// refills
@ -831,15 +831,15 @@ class HellaCache extends L1HellaCacheModule {
writeArb.io.in(1).bits.wmask := ~UInt(0, nWays)
writeArb.io.in(1).bits.data := narrow_grant.bits.data(encRowBits-1,0)
readArb.io.out.ready := !narrow_grant.valid || narrow_grant.ready // insert bubble if refill gets blocked
readArb.io.out <> data.io.read
data.io.read <> readArb.io.out
// writebacks
val wbArb = Module(new Arbiter(new WritebackReq, 2))
prober.io.wb_req <> wbArb.io.in(0)
mshrs.io.wb_req <> wbArb.io.in(1)
wbArb.io.out <> wb.io.req
wb.io.meta_read <> metaReadArb.io.in(3)
wb.io.data_req <> readArb.io.in(2)
wbArb.io.in(0) <> prober.io.wb_req
wbArb.io.in(1) <> mshrs.io.wb_req
wb.io.req <> wbArb.io.out
metaReadArb.io.in(3) <> wb.io.meta_read
readArb.io.in(2) <> wb.io.data_req
wb.io.data_resp := s2_data_corrected
releaseArb.io.in(0) <> wb.io.release
@ -866,7 +866,9 @@ class HellaCache extends L1HellaCacheModule {
val s2_data_word = Mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass)
val loadgen = new LoadGen(s2_req.typ, s2_req.addr, s2_data_word, s2_sc)
amoalu.io := s2_req
amoalu.io.addr := s2_req.addr
amoalu.io.cmd := s2_req.cmd
amoalu.io.typ := s2_req.typ
amoalu.io.lhs := s2_data_word
amoalu.io.rhs := s2_req.data

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@ -370,7 +370,7 @@ class Rocket extends CoreModule
csr.io.exception := wb_reg_xcpt
csr.io.cause := wb_reg_cause
csr.io.retire := wb_valid
csr.io.host <> io.host
io.host <> csr.io.host
io.fpu.fcsr_rm := csr.io.fcsr_rm
csr.io.fcsr_flags := io.fpu.fcsr_flags
csr.io.rocc <> io.rocc

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@ -29,20 +29,20 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
dcArb.io.requestor(0) <> ptw.io.mem
dcArb.io.requestor(1) <> core.io.dmem
dcArb.io.mem <> dcache.io.cpu
dcache.io.cpu <> dcArb.io.mem
ptw.io.requestor(0) <> icache.io.ptw
ptw.io.requestor(1) <> dcache.io.ptw
core.io.host <> io.host
core.io.imem <> icache.io.cpu
io.host <> core.io.host
icache.io.cpu <> core.io.imem
core.io.ptw <> ptw.io.dpath
//If so specified, build an FPU module and wire it in
params(BuildFPU)
.map { bf => bf() }
.foreach { fpu =>
fpu.io <> core.io.fpu
core.io.fpu <> fpu.io
}
// Connect the caches and ROCC to the outer memory system