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Chisel3: bulk connect is not commutative

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We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
This commit is contained in:
Andrew Waterman
2015-08-01 21:11:25 -07:00
parent 6c0e1e33ab
commit 52fc34a138
4 changed files with 34 additions and 32 deletions
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8
rocket/src/main/scala/tile.scala
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@ -29,20 +29,20 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
dcArb.io.requestor(0) <> ptw.io.mem
dcArb.io.requestor(1) <> core.io.dmem
dcArb.io.mem <> dcache.io.cpu
dcache.io.cpu <> dcArb.io.mem
ptw.io.requestor(0) <> icache.io.ptw
ptw.io.requestor(1) <> dcache.io.ptw
core.io.host <> io.host
core.io.imem <> icache.io.cpu
io.host <> core.io.host
icache.io.cpu <> core.io.imem
core.io.ptw <> ptw.io.dpath
//If so specified, build an FPU module and wire it in
params(BuildFPU)
.map { bf => bf() }
.foreach { fpu =>
fpu.io <> core.io.fpu
core.io.fpu <> fpu.io
}
// Connect the caches and ROCC to the outer memory system