riscv/rocket-chip
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Chisel3: bulk connect is not commutative

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We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with.  Should make
for lively debate.
This commit is contained in:
Andrew Waterman
2015-08-01 21:11:25 -07:00
parent 6c0e1e33ab
commit 52fc34a138
4 changed files with 34 additions and 32 deletions
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2
rocket/src/main/scala/rocket.scala
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@ -370,7 +370,7 @@ class Rocket extends CoreModule
csr.io.exception := wb_reg_xcpt
csr.io.cause := wb_reg_cause
csr.io.retire := wb_valid
csr.io.host <> io.host
io.host <> csr.io.host
io.fpu.fcsr_rm := csr.io.fcsr_rm
csr.io.fcsr_flags := io.fpu.fcsr_flags
csr.io.rocc <> io.rocc